Home > Products > Synopsys' Design Compiler Graphical shortens design schedule at Oticon

Design

Synopsys' Design Compiler Graphical shortens design schedule at Oticon

27th July 2010

Synopsys Inc

ES Admin

0 0

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Oticon taped out the digital signal processor (DSP) chipset for their next generation hearing-aid devices ahead of schedule using Synopsys' Design Compiler(tm) Graphical RTL Synthesis, a key component of the Galaxy(tm) implementation platform. Engineers at Oticon, a world leader in the design, development and manufacture of hearing aids, needed to add new features to the next generation DSP without increasing design area and while maintaining a very tight schedule. This was especially challenging due to the routing congestion caused by the added functionality, which could have led to multiple design iterations and a longer design schedule. To alleviate this congestion, Oticon's RTL designers deployed the congestion optimisations in Design Compiler Graphical during RTL synthesis, resulting in an easy to route netlist and predictable design closu

We strive to deliver innovative hearing-aids to our customers, and minimising the size and power consumption of these devices is critical to our success, said Mogens Balsby, director of Silicon Engines at Oticon. As we enhanced the feature set of our next generation DSP, we saw severe routing congestion due to tight chip area requirements. By utilising Design Compiler Graphical's congestion optimisations, we eliminated this routing congestion upfront without having to increase our chip area, and taped out successfully ahead of schedule.

Design Compiler Graphical extends DC Ultra(tm) topographical technology to predict routing congestion hot spots early in the design flow, providing designers with visualisation of congested circuit regions and performing specialised synthesis optimisations to minimise congestion in these areas. This enables RTL designers to avoid wire routing congestion problems that occur during detailed routing and eliminate costly design iterations.

Additionally, Design Compiler Graphical provides access to IC Compiler's design planning capabilities from within the synthesis environment, giving RTL designers the ability to explore and converge on an optimal floorplan faster. It also produces physical guidance to IC Compiler physical implementation, tightening timing and area correlation to 5 percent while speeding up IC Compiler placement by 1.5X. By enabling RTL designers to achieve an optimal floorplan efficiently and passing physical guidance to IC Compiler, Design Compiler Graphical can double the productivity of the entire synthesis and place and route flow.

Shorter, more predictable design schedules help our customers bring competitive products to market faster, said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. Synopsys continues to deliver innovative RTL synthesis technologies, such as congestion optimisation, floorplan exploration and physical guidance to IC Compiler, enabling companies like Oticon to meet their challenging design and time to market goals.