Cadence Collaborates with Samsung Foundry to Deliver Design-for-Manufacturing Solution for 32-, 28- and 20-Nanometer Chip Design

The new flows address both random and systematic yield issues, providing customers with a proven foundry option for advanced-node designs built on the Cadence Encounter® digital and Cadence Virtuoso custom/analog implementation solutions.

The unique Cadence in-design approach to Silicon Realization moves traditional DFM steps into the implementation stage of digital and custom chip design. This approach is aimed at boosting productivity, predictability and profitability while reducing risk. The DFM flows developed at Samsung Foundry leverage multiple groundbreaking technologies, including Cadence Pattern Classification and Search, Cadence CMP Predictor, Cadence Litho Physical Analyzer and Cadence Yield Analyzer and Optimizer.

“As we expand our customer base at advanced process nodes, customers require various design flows,” said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics, “By teaming with Cadence to build a strong foundry ecosystem for advanced node designs, we’ve achieved numerous benefits we can pass along to our customers such as reducing risk and speeding time to market. We’ve enjoyed great success at 32 and 28 nanometers with Cadence, and we have now extended our advanced DFM flow to 20 nanometers as well.”

Manufacturing complexity is growing exponentially at advanced nodes, and it impacts design cycle time and time to yield compared to previous nodes. With the new infrastructure optimized for advanced nodes, Samsung Foundry is able to use the hierarchical design approach and pattern matching to perform effective and accurate systematic failure analysis. And the Cadence production-proven in-design DFM prevention and optimization in Cadence Encounter® digital and Cadence Virtuoso® custom/analog implementation solutions enables first-time-correct silicon.

The Cadence pattern classification technology allows Samsung Foundry to classify the yield detractor patterns into easily usable pattern libraries. The infrastructure enables Samsung Foundry’s customers to leverage the in-design and signoff pattern matching with automated fixing flows in Encounter and Virtuoso. Another new innovation from this collaboration is the development of a Chip-based CMP analysis flow to enable early convergence of topography yield issues in advanced digital and custom designs.

“As the provider of cutting-edge technologies and methodologies for leading foundries, we worked closely with Samsung Foundry to integrate our robust DFM suite, which continues to gain momentum as the advantages of in-design DFM become increasingly evident,” said Tom Beckley, senior vice president, Custom IC and Signoff, Silicon Realization Group at Cadence. “The flows and underlying infrastructure our companies created together can provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.”