The controller integrates Ethernet MAC and PHY with a high performance SRAM-like slave interface. The simple but functional host bus interface provides a glue-less connection to most common 16 and 32-bit microprocessors and microcontrollers. It includes large transmit and receive FIFOs with a high speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the device’s memory buffer architecture allows the most efficient use of memory resources by optimising packet granularity.
The device’s numerous power management and wake-up features mean it can operate in a reduced power mode, and can then be programmed to issue an external wake signal via several methods. This is ideal for triggering system power up using remote Ethernet wake-up events. It is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-T compliant, and supports HP Auto-MDIX.