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ASSET InterTech White Paper exploring signal integrity problems on high-speed buses

28th November 2012

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Whitepaper

A new white paper from ASSET InterTech points out how increasing bus speeds on circuit boards could create havoc for signal integrity on those buses, in turn degrading the bus’ throughput performance. Each new generation of a high-speed bus typically runs at a higher signal frequency, but this decreases the margin for error on the bus, making it more sensitive to disruptions from jitter, inter-symbol interference, crosstalk and other factors.

To avoid potential problems on high-speed buses like DDR3, PCI Express, Intel QPI, Serial ATA, USB and others, bus performance must be validated during each phase of a system’s life cycle, including design/development, manufacturing and as an installed system in the field. Unfortunately, effectively and economically validating the signal integrity on a high-speed bus has become more difficult as the limitations of legacy probe-based test equipment such as oscilloscopes have become more obvious in recent years. Now though, non-intrusive software-driven test methods based on embedded instrumentation are providing alternative validation solutions that are more cost-effective and deliver observed signal integrity data.