Microsemi reveals its embedded world programme
Semiconductor solutions company, Microsemi, has announced it will be participating at embedded world 2018 in Nuremberg, Germany, from 27th February to 1st March. The company has assembled a group of technical experts to showcase how the company’s solutions, including its Mi-V Embedded Ecosystem, PolarFire field programmable gate array (FPGA) family and RISC-V embedded processor, help application engineers tackle the unique challenges associated with embedded systems.
Microsemi will be hosting five presentation topics at booth 1-431 starting at 10am each day of embedded world, with a new session beginning each hour. Sessions include:
- 'PolarFire FPGA Solutions', which introduces the company’s award-winning PolarFire FPGAs, including device architecture, devices/packages, available intellectual property (IP), solutions and demonstration designs;
- 'Introduction and Update on RISC-V', where the RISC-V Foundation will present the basics of RISC-V, a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, and is now set to become a standard open architecture under the governance of the RISC-V Foundation;
- 'Mi-V RISC-V Ecosystem', which highlights Microsemi’s RISC-V ecosystem components and roadmap;
- 'Machine Learning/Artificial Intelligence', where ASIC Design Services will explain the multi-layer convolutional neural network Core Deep Learning IP; and
- 'Walnut Digital Security', where SecureRF will present the capabilities of its Walnut DSA security IP.
In addition, Microsemi experts will be on hand in booth 1-431 to discuss and demonstrate a number of innovative new products and solutions, including:
- PolarFire FPGA’s Low Power: Using the PolarFire Splash kit, this demonstration will showcase the low power of Microsemi’s PolarFire FPGA.
- PolarFire SmartDebug Eye Diagram: Using the PolarFire Evaluation board, Microsemi’s experts will show the eye diagram of the transceiver on the MPF300T.
- Mi-V RISC-V: The Microsemi Mi-V RISC-V core will be running on both PolarFire and IGLOO2 FPGAs with various example designs such as hello world, a touch screen demo, and WiFi web server.
- PolarFire HDMI 2.0: Using the high-speed transceivers of PolarFire FPGAs, this IP will demonstrate PolarFire’s ability to receive and transmit HDMI 2.0b video.
- ASIC Design Services AI/ML: This machine learning/artificial intelligence IP from ASIC Design Services will showcase the ability of PolarFire FPGAs to recognise people.
- SecureRF Security: This design showcases SecureRF’s Walnut DSA IP running on a Mi-V RISC-V core in a SmartFusion2 FPGA.
Microsemi’s Director of FPGA marketing, Ted Marena, will also provide two presentations at embedded world, titled, 'High-Speed Interfaces in Cost-Optimised FPGAs' and 'High Resolution Display Interfaces Leveraging Cost-Optimised FPGAs', while Tim Morin, Microsemi’s Director of marketing, will present 'Running RTOS on RISC-V' as part of the RISC-V class at embedded world.
embedded world 2018 is the world’s leading meeting place for the embedded systems community where experienced developers come to share their knowledge and help others to convert their ideas and inventions into real products. Microsemi’s PolarFire FPGA applications for industry 4.0 as well as those for the broader industrial market are suited for embedded systems professionals, with applications including factory automation, industrial Ethernet switches, video and image processing, machine vision, programmable logic controllers, portable test equipment and medical.
Microsemi will be located in hall 1, booth 431, at the Nuremberg Messe, located at Karl-Schoenleben-Strasse, 90471 in Nuremberg, Germany. Marena’s 'High-Speed Interfaces in Cost-Optimised FPGAs' presentation and 'High Resolution Display Interfaces Leveraging Cost-Optimised FPGAs' presentation, as well as Morin’s 'Running RTOS on RISC-V' presentation, will all take place in the Conference Centre NCC Ost.
Microsemi’s involvement in the conference will take place 27th February to 1st March during show hours. (27-28th February from 9am to 6pm and 1st March from 9am to 5pm).
Marena’s 'High-Speed Interfaces in Cost-Optimised FPGAs' presentation will take place from 11-11:30am on Wednesday 28th February and his 'High Resolution Display Interfaces Leveraging Cost-Optimised FPGAs' presentation will take place from 2:35-2:55pm on Thursday 1st March.
Morin’s 'Running RTOS on RISC-V' presentation will take place from 9:30-10am on Tuesday 27th February.