Advanced mobile application requires reduced chip size and lower power consumption. Process migration is a solution to meet the demand, however, shorter channel length tends to cause current leakage. Both reduction of power consumption and chip size shrinkage require controlling channel impurity concentration and fining layout.
Toshiba has established and applied new platform technology for a new activation sequence using flash lamp anneal, optimizing impurities in the ion implantation process, and applying Hafnium incorporated insulators and DFM (design for manufacturing) technologies. Doubling the flash lamp anneal process boosted both the PMOS and NMOS performance. Doping germanium with nitrogen in the ion implantation process minimized concentration in the channel area, which contributes to higher transistor performance. Hafnium incorporated insulators improve drive current by increasing threshold voltage without excess concentration of channel impurities. Application of DFM technologies enabled aggressively scaled layout with lower lithographic defects.
Toshiba will further enhance development of low-power-consumption technology for advanced generations.