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Imec and Synopsys Expand FinFET Collaboration to 10Nanometer Geometry

12th December 2012

IMEC

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The collaboration builds on extensive work done at 14-nm and several other process geometries, and will calibrate Synopsys’ Sentaurus TCAD models to support the next-generation FinFET devices. The collaboration will include 3-D modeling of new device architectures and materials that will enable the semiconductor industry to continue to deliver products with higher performance and lower power consumption.

Imec is partnering with leading IC companies for research in advanced CMOS scaling. Device scaling beyond feature-size reduction requires research on a range of new technologies, including new materials, device architectures, 3-D integration, and photonics. The collaboration between imec and Synopsys specifically focuses on the development and optimization of new device architectures based on FinFETs and tunnel FETs. At this week’s IEEE International Electron Devices Meeting, imec presented a paper on the use of stressors to boost carrier mobility, which is critical to scale FinFET devices at 10-nm and beyond. Insights and understanding obtained through the usage of Synopsys’ TCAD tools will allow imec to accelerate this research.

“This expanded collaboration with imec enables us to extend Synopsys’ industry-leading TCAD simulation tool for next-generation FinFET device modeling and development,” said Howard Ko, general manager and senior vice president of the silicon engineering group at Synopsys. “Imec is recognized worldwide for its expertise, excellent research facilities and industry focus, and our partnership will help to further advance our TCAD solutions.”