LPC1200 product platform is specifically designed with flexibility and customization in mind, making it particularly suitable for a wide variety of energy-efficient system and power management requirements. For example, in advanced washing machines, the LPC1200 can control the motor systems, handle the user interface, monitor system power consumption, and manage off-board communications in a simple, integrated and energy-efficient solution. Its high current GPIO can directly control TRIACs without the need for external transistors, further reducing footprint and costs.
“We are pleased to team up with NXP in defining specifications for the LPC1200,” said Stefano Frattesi, Innovation for Design manager at Indesit Company, a leading manufacturer of energy efficient smart appliances. “The Cortex-M0 32-bit performance and the new features of the LPC1200 microcontroller will enable an innovative future-proof platform for next generation white goods, while continuously improving robustness and reliability.”
“The LPC1200 is a compelling solution for Industrial Control system designs,” said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. “The combination of Cortex-M0 processor with configurable peripherals cannot be matched by any legacy 8-bit systems.”
Designed for smart appliances and white goods In tomorrow’s energy-efficient smart appliance designs, the CPU will not only have to manage the user interface and control, but will also increasingly be required to drive multiple motor systems, as well as continuously measure current and voltage to calculate active power with high accuracy. The LPC1200 series meets these demanding system requirements with its high score of over 45 in CoreMark™ CPU performance benchmark testing, equivalent to 1.51/MHz.
For high volume applications, the LPC1200 platform can provide rapid delivery of application-specific solutions (ASSP) for a wide range of industrial control requirements, through flexible interconnections between the interrupt controller, DMA sub system, on-chip peripherals and GPIO. By recognizing external and internal events and carrying out pre-defined tasks without CPU intervention, the CPU load is dramatically reduced, allowing the CPU to remain in power down longer.
Maximizing flexibility, efficiency and robustness The NXP LPC1200 offers over 50 Flash and SRAM memory combinations, giving designers maximum flexibility to optimize the features and product cost within the same footprint. In addition, the small 512 Byte erase sector of the Flash memory brings multiple design benefits, such as finer EEPROM emulation, boot-load supports from any serial interface, and ease of in-field programming with reduced on-chip RAM buffer requirements.
Taking advantage of the ARM Cortex-M0 v6-M 16-bit Thumb instruction set, the LPC1200 has up to 50 percent higher code density compared to common 8/16-bit microcontrollers performing typical tasks. The Cortex-M0 efficiency also helps the LPC1200 achieve lower average power for similar applications. Further, NXP’s unique SRAM architecture allows the LPC1200 to minimize power by automatically setting each of the 2KB low-power blocks into its lowest possible power mode.
Designed for high reliability and robustness, the LPC1200 is rated as high immunity, based on the Electrical Fast Transient test conducted by Langer EMV-Technik GmbH per IEC61697-1 recommendations. Electrostatic Discharge protection is rated at 8kV.
Innovative peripherals for industrial control The LPC1200 comes with a set of peripherals that are specifically suited for appliances and industrial design:
* A Windowed Watchdog Timer with an independent internal oscillator source, designed to comply with IEC 60730 Class B safety requirements for white goods
* A Programmable Digital Filter on all GPIO pins allowing better control of signal integrity for industrial applications
* I2C with Fast-mode Plus feature with 10x higher bus-drive capability compared to typical I2C I/O drives, allowing for twice as many devices on the same bus, as well as longer transmission distances
* Optimized ROM-based divide library for Cortex-M0 offering several times the arithmetic performance of software-based libraries, as well as a highly deterministic cycle time combined with reduced Flash code size
* Dual analog comparators with 32 levels of voltage reference, edge and level detection and output feedback loop supporting multiple states, such as monostable, astable or simple set/reset
The LPC1200 extends NXP’s Cortex-M0 microcontrollers portfolio with up to 55 GPIOs, multiple timers/serial channels, and new onboard peripherals including RTC, DMA, CRC and 1 percent internal oscillator, which provides the required accuracy for Baud rate generation. Upcoming LPC1200 derivatives will also include additional features, such as an integrated 40x4 segment display driver.