development engineers under immense pressure to reduce the cost of design, developers’ options are being reduced, often feeding an artificial development scenario that touts the need for 32-bit microcontrollers. However, 16-bit microcontrollers can still penetrate the 32-bit microcontroller application field, covering the characteristics listed above while being more cost effective.
The brushless DC motor (BLDC) or the permanent magnet AC motor (PMAC) are increasingly finding their way into different applications for present day drive technology. This is mostly because of the way these motors operate and their performance efficiency in producing torque and speed, as well as their long life.
In addition to the typical control characteristics of these motors, developers must also take into account the increasing complexity and a growing demand for even higher system quality. When developing a platform solution, the need lies in higher system safety and reliability coupled with design and application flexibility, which results in the possible options open to a development engineer becoming rather narrow and prescribed.
Here the decisive criterion is a highly sensitive, cost optimised development. Such systems demand deployment of microcontrollers able to guarantee system design flexibility. Cost reduction through elimination of external components plays an important role in selecting a suitable microcontroller.
With the 16-bit RL78 series, Renesas Electronics offers a family of microcontrollers adapted to various market application requirements. The basic RL78 family architecture is a mix of the 78K0R family and the R8C, delivering 1.27 DMIPS/MHz performance. At its maximum operating frequency, 32MHz, its current consumption is only 70µA/MHz. The minimum instruction execution time can be changed from high-speed 0.03125µs (at 32MHz operation) using high-speed on-chip oscillator clock to ultra-low-speed 30.5µs (at 32.768kHz operation) using subsystem clock. The diverse instruction set has 87 instructions of which 56 percent can be executed within one clock cycle. Figure 1 shows the distribution of the RL78 instruction cycle count.
Figure 1: Instructions execution cycle count distribution
The RL78 CISC Harvard architecture has a three-stage pipeline, four register banks of 8 x 8-bit registers each, and a 16-bit barrel shifter. The DSP functions as a 16 x 16-bit signed and unsigned multiplier, with 32 by 32-bit division as well as the so-called MAC (Multiply and Accumulate). This has proven to be extremely useful in executing complex algorithms and computation intensive operations. The MAC instruction can execute a 16 x 16-bit multiplication and a 32-bit addition within two clock cycles and is ideally suited for filter designs.
On top of this, variety of flexible peripherals like DTC (Data Transfer Controller) and the ELC (Event Link Controller) contribute towards reducing the CPU workload. These peripherals allow configuration of a hardware loop, which can react to external events in real time without having to go through standard processing by CPU. Figure 2 shows all functional blocks, which characterise the G14 group of the RL78 family. The data flash can operate in the background parallel to the application software execution by the CPU and thus can store important system parameters and serve as E2PROM replacement. The high-speed oscillator clock ranges from 64MHz, 32MHz, and 24MHz right down to 1MHz and has an accuracy of +/- 1% over the complete temperature and voltage range. Please note though that the 64MHz maximum internal clock is available only for the 16-bit Timer RD.
Figure 2: RL78/G14 System build-up
The CPU and the rest of the peripherals operate in the high-speed range at the maximal clock rate of 32MHz. Moreover, the RL78 family offers some special hardware safety functions. These functions support the realisation of and compliance with the IEC60730 safety standards ideally and lead to reduced CPU load during tests. Protection functions, like RAM or SFR write protection, which cannot be executed in software, have also been implemented in other relevant on-chip functional blocks.
The focus with regard to the drive and control of a BLDC- or PMAC-motor lies on the internal structure of the G14 family peripherals like 3-Phase Timer RD, the A/D Converter and the already mentioned peripherals like DTC and ELC.
The G14 Analog Digital (A/D) Converter is a 10-bit resolution converter with a minimum conversion time of 2.1µs. In addition to the software, the A/D conversion can also be triggered through other internal peripherals. One of the possible trigger sources is the timer module deployed in combination with the ELC module. The A/D conversion voltage range lies between 1.6V and 5.5V. The module has an internal reference voltage source of 1.44V, which can be used as either reference or input voltage. Additionally, the module also has an internal temperature sensor, which provides the measured temperature value in one of the A/D converter results registers.
The DTC module allows a memory-to-memory data transfer without CPU interaction. Twenty-four channels are available for this; the transfer is triggered through an interrupt generated by one of the peripherals. In the process, source and destination addresses serve to transfer the data from and to the corresponding addresses. The selected mode as well as the source and destination transfer address is stored in the DTC module control area. This control area is mapped to the RAM and is defined by the DTCBAR register. In total, there are thirty-one sources with programmable priorities to activate the DTC transfer. The maximum amount of data, which can be transferred in 16-bit data transfer mode is 512bytes. The DTC module supports two transfer modes; normal- and repeat-transfer modes. In normal mode, the DTC module stops after each single transfer of the corresponding data. Contrary to that, in repeat mode the data transfer is continuous, the destination address is automatically initialised and the register value is reloaded. In this case, the amount of data (count) to be transferred can be programmed in the DTC transfer count register. The DTC signals the end of the data transfer by an interrupt. In normal mode an interrupt is generated after every data transfer, in the repeat mode it is generated only after complete transfer of the programmed data amount. The DTC module is operational also in HALT or SNOOZE standby modes. This guarantees the data transfer function even in the power save mode and can be used to wake-up the CPU. Figure 3 shows an example of data transfer function from A/D converter to the RAM. It demonstrates the advantages of using the DTC function compared to the standard process via an interrupt.
Figure 3: Example showing the advantages of using the DTC function compared to the standard process via an interrupt
Event Link Control
The ELC module allows programmable connections (links) between output events from each peripheral function. The block diagram of ELC module is shown in Figure 4.
Figure 4: Block diagram of the ELC module
These internal peripheral connections (links) allow direct coordination of operations between peripheral functions without CPU interaction. This reduces the interrupt processing load for the CPU drastically and the software can be size optimised. Reduction of the interrupt processing load for the CPU as shown in Figure 5 and the direct control over the I/O ports improves the overall real time behaviour of the system. Depending upon the G14 group device type selected, the ELC module can link from 20 types (in 30- up to 64-pin package devices) up to 26 types (in 80- and 100-pin package devices) of event signals between the peripherals.
Figure 5: Comparison between standard processing and an ELC Module
The Timer RD module consists of two 16-bit timers, the Timer RD0 and Timer RD1 with four I/O pins each. In addition to the Input-capture or Output-compare functions, this module offers three selectable PWM modes as follows:
-Reset Synchronous PWM mode
-Complementary PWM mode
The second mode outputs six mid-centred and weighted triangular phase waveforms, automatically loaded with a pre-defined dead time. The waveform of these complementary 3-phase PWM is shown in Figure 6.
Figure 6: Complementary PWM Mode with Dead Time
All three modes however require the combination of both timers. The timer output pin functions depend on the timer mode selected.
The Timer RD module is equipped with a shut-off mechanism, which can deactivate and switch the module outputs into HI-Z state. This allows the system to be switched off on current overload. It is also possible to control this safety mechanism through the already described ELC module. Thus, the switching off of the outputs can also be executed through other events. An example of this would be the use of the implemented comparator. It has two channels and together with the so-called Window-function, it is used for power monitoring. This ensures that the system power-supply-circuit (inverter) is protected against over current and voltage drops.
Through a combination of above-mentioned modules it is possible to devise a standalone mechanism that can automatically control the processes at hardware level. The CPU is not needed for this coordinating task and is thus relieved. Instead, the CPU time can be used to process the mathematical computations or to evaluate the communications. An example of one such possible combination of these modules is shown in Figure 7.
Figure 7: Possible module combinations and their automated links
The Timer RD generates the necessary 3-phase PWM signals to drive the BLDC or PMSM motor. The system variables data transfer can take place in an automated hardware loop, improving the real time processing and leading to optimised system control quality and responsiveness. The automation of the data transfer takes place through the peripheral hardware links with the ELC and DTC modules. The Starting Timer RD causes the ELC module to also start the Timer RJ in interval mode, which in turn generates programmable time triggers for the A/D converter. With that, the acquisition of the current value, the BEMF, and the measured voltage data through PWM can be synchronised within a single cycle.
Noise has little or no influence on signal measurements at all. Consequently, reduction or total elimination of external filter circuits and internal software filter calculations is possible. The CPU can thus be relieved from the load of external data acquisitions, transfers and event processing: it can instead be deployed to process control computation and evaluation of available data. How such an effective and economical system build-up works, is demonstrated by a demonstration kit that offers Field Oriented Control (FOC) algorithm versions for a three or single–shunt sensorless PMSM motor. An open source software library with all necessary drive and control functions is available. In addition to the complete documentation and the PCB layout data, a GUI is also offered. The developer can program all relevant system parameters by himself to evaluate and optimise the application. This not only ensures the deployment of a customer specific motor for a given application but also guarantees fast and cost optimised development.