The Cadence analogue/mixed-signal (AMS) IC design flow has achieved certification for UMC’s 28HPC+ process technology. With this certification, mutual Cadence and UMC customers have access to a comprehensive AMS solution for designing automotive, industrial internet of things (IoT) and artificial intelligence (AI) chips using 28HPC+ technology.
The complete AMS flow, based on UMC’s Foundry Design Kit (FDK), includes an actual demonstration circuit with a highly automated circuit design,layout, signoff and verification flow that enables more seamless design on 28HPC+.
The flow incorporates the proven custom/analogue, digital and verification platforms, and supports the broader Cadence Intelligent System Design strategy, accelerating SoC design excellence.
It features integrated standard cell digital capabilities that are well suited for digitally assisted analogue designs.
The complete, certified AMS flow includes the Virtuoso Analogue Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Space-Based Router, Spectre Accelerated Parallel Simulator (APS), Spectre AMS Designer with integrated Xcelium Parallel Logic Simulation,Voltus-Fi Custom Power Integrity Solution, Innovus Implementation System, Quantus Extraction Solution and Physical Verification System (PVS).
The flow provides the following:
“In collaboration with UMC, Cadence has delivered a certified, integrated flow for AMS design at 28HPC+ technology based on Cadence’s industry-leading custom/analog, digital and signoff, and verification platforms,” said Wilbur Luo, vice president, product management in the Custom and PCB Group at Cadence. “This certification drives SoC design excellence and allows UMC customers to take advantage of the most advanced tool feature sets for circuit design, performance and reliability verification, automated layout, and block and chip integration, enabling them to design automotive, industrial IoT and AI applications with confidence.”
UMC's production-ready 28HPC+ process utilises a high-performance High-k/Metal Gate stack to support broad device options for increased flexibility and performance requirements, targeting a wide range of products such as application processors, cellular basebands, Wi-Fi, DTV/STB, mmWave, etc.
The High-k-/metal gate stack and abundant options for core device Vt, various memory bit-cells and under drive/overdrive I/O capabilities help SoC designers realise unmatched cost, performance and battery life.
“Through our collaboration with Cadence, we have developed a comprehensive and unique offering that utilises the Cadence AMS flow and a UMC design kit to offer a reliable and efficient flow for designing with our 28HPC+ process technology,” said T.H. Lin, director of the IP Development and Design Support division at UMC. “Leveraging the capabilities of this flow, which was created with the intention of providing detailed instructions so that users could improve productivity with UMC’s process, customers can deliver innovative, next-generation products to market faster.”