Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Freescale Semiconductor, a global leader in the design and manufacture of semiconductors for the automotive, consumer, industrial and networking markets, has licensed Synopsys' DesignWare® IP for Freescale's system-on-chip (SoC) designs.

Synopsys announced that Wilocity has successfully taped-out its multi-gigabit Wireless Gigabit Alliance-compliant system-on-chip (SoC) utilizing Synopsys' broad portfolio of high-quality DesignWare® IP and assistance from Synopsys Professional Services. The DesignWare IP used in the SoC included PCI Express, embedded memories and logic libraries. Wilocity's SoC is based on the Wireless Gigabit Alliance (WiGig) and IEEE802.11ad draft specificatio...

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the release of its next-generation DesignWare Data Converter IP solutions, which deliver more than 50 percent improvement in power with smaller area compared to the previous generation of data converters.

Synopsys, Inc. announced that the Industrial Technology Research Institute of Taiwan (ITRI) has adopted Synopsys' TCAD Sentaurus simulation software to support its research and development of silicon carbide (SiC) semiconductor devices.

Synopsys, Inc. today announced that Amlogic has selected Synopsys' CustomSim solution for mixed-signal verification of its high-performance multimedia system-on-chips (SoCs).

Synopsys, Inc. today announced the availability of enhancements to its CODE V optical design and analysis software.

Synopsys, Inc. today announced Synplify Pro, Synplify Premier and Synphony synthesis support for Xilinx's latest ISE Design Suite (IDS) 13, which provides support for their 28-nanometer (nm) 7 series FPGAs. Synopsys' advanced FPGA synthesis tools include a hierarchical project manager that enables team-design collaboration with a mixed bottom-up/top-down approach that is highly integrated with Xilinx's SmartGuide incremental place & route (P&R) t...

Synopsys, Inc. today announced that Yokogawa Electric Corporation used Synopsys Processor Designer to achieve ultrafast ladder program processing performance for their latest FA-M3V programmable logic controller (PLC). Yokogawa also saved significant development and verification effort with Processor Designer since the tool automatically generates software development tools such as C-compiler, assembler/linker, debugger and the instruction set s...

Synopsys, Inc. and Xilinx, Inc. today announced the availability of the FPGA-Based Prototyping Methodology Manual (FPMM), a practical guide to using FPGAs as a platform for system-on-chip (SoC) development. The FPMM captures valuable design and verification expertise contributed by engineering teams from BBC Research & Development; Design of System on Silicon, S.A. (DS2); Freescale Semiconductor; LSI, Inc.; NVIDIA Corp.; STMicroelectronics; and T...

Synopsys Inc introduced Proteus LRC for lithography verification. Proteus LRC provides comprehensive, process-window-aware checking features to identify locations in a design that are sensitive to process variations, thereby enabling corrective action to be taken prior to committing a design to manufacture. Proteus LRC is integrated into the Proteus Mask Synthesis flow and is targeted for use by OPC and mask data preparation groups at semiconduct...

Synopsys Inc announced the availability of the HAPS-600 series, the highest capacity extension of the HAPS family of FPGA-based prototyping systems. The HAPS-600 series extends FPGA-based prototyping capacity up to 81 million ASIC gates equivalent, enabling early software development for larger SoC projects. Like the HAPS-60 products, the HAPS-600 series is based on Xilinx Virtex-6 LX760 FPGA devices and offers performance up to 200 megahertz.

Synopsys Inc today announced that it is the first IP provider to support the final version of the PCI Express 3.0 base specification, recently released by the PCI Special Interest Group.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that John Chilton, senior vice president of marketing and corporate development, will speak at the Morgan Stanley Technology, Media & Telecom Conference in San Francisco, on Mar. 1, 2011.

Synopsys announced the immediate availability of the silicon-proven DesignWare Data Converter IP for SMIC's popular 65-nanometer (nm) Low Leakage (LL) process technology, enabling designers to improve their chips' power efficiency and ease their integration efforts. Synopsys is the first IP provider to offer a comprehensive portfolio of high-performance data converter IP solutions consisting of analog-to-digital converters (ADCs) and digital-to-a...

Synopsys and Varian Semiconductor Equipment Associates, Inc. (Nasdaq: VSEA), the leading producer of ion implantation equipment used in the manufacture of semiconductors, today announced a collaboration to develop Technology CAD (TCAD) models for cryogenic ion implantation. By enabling faster optimization of the cryogenic implant process through simulation, the models derived from this collaboration will speed up process development of advanced C...

Synopsys announced the release of its enhanced DesignWare Universal DDR Memory Controller, which delivers up to 30 percent lower latency and offers up to 15 percent higher throughput than the previous generation controller. The DDR Memory Controller offers new features such as high-priority bypass and configurable 'look-ahead.' The high-priority bypass option allows designers to improve latency by bypassing the scheduling algorithm, allowing imme...

Synopsys announced the broad availability of Platform Architect with Multicore Optimization Technology, a new solution for performance analysis and early definition of multicore system architectures in SystemC. Using Platform Architect with Multicore Optimization Technology, designers of SoCs, chipsets and systems can capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance m...

Synopsys today announced the verification FastForward migration program. The program helps Cadence Incisive and Mentor Graphics Questa users to migrate to the VCS functional verification solution and benefit from its superior technologies. These include: innovative performance engines; the industry's broadest SystemVerilog support for VMM, OVM, and the UVM methodologies; a powerful constraints solver; new coverage closure technologies; unique l...

Synopsys announced new extensions to its open source-licensed Interconnect Technology Format (ITF) which enables modeling of more complex device structures and interconnect layers for parasitic extraction tools at 28-nanometer (nm) and below process technologies. Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) to define th...

Synopsys announced the availability of the latest release of IC Compiler, a key component of the Galaxy Implementation Platform. This development caps a year of leading innovations in physical design productivity. For two years in a row, IC Compiler has won an EDN Innovation Award. In 2010 it won for In-Design Physical Verification. The IC Compiler 2010.12 release advances this capability, making automatic DRC repair up to 7X faster. This latest ...