With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros. To simplify this process, Cadence Design Systems has introduced the Virtuoso Liberate AMS characterisation solution which automates standard Liberty model creation for large mi...

Cadence's Verification IP (VIP) supports all popular 3D memory standards, including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP allows designers to accelerate the verification of memory interfaces and achieve earlier SoC verification closure for compute server applications, mobile devices, high-performance graphics and network applications.

Claimed to reduce the effort required by automotive designers to prepare for ISO 26262 compliance by up to 50%, Cadence Design Systems has introduced an automotive functional safety verification solution. The fault injection and safety verification technologies, which help automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level, are an expansion to the company’s Incisive functional ...

The industry’s first MIPI SoundWireSM Controller Intellectual Property (IP) has been released by Cadence. SoundWire is a new digital audio interface specification from the MIPI Alliance that enables bi-directional digital communication with a focus on low complexity and low gate count, making it attractive to many mobile design applications.

Cadence Design Systems, Inc. and ARM today announced the signing of a multi-year Technology Access Agreement. Expanding upon the successful EDA Technology Access Agreement signed in May 2014, this new agreement gives Cadence rights to access to existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink System IP, ARM Artisan physical IP, and ARM POP IP. This partnership enables ARM and Cadence to continue providing customers with adva...

Cadence Design Systems, Inc announced that its digital and custom/analog tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process, enabling systems and semiconductor companies to take advantage of the 15 percent speed improvement with the same total power compared to 16nm FinFET, or 30 percent total power reduction at the same speed compared to 16nm FinFET. 16FF+ V1.0 certification is on track to b...

To enable the rapid development of IoT and wearable devices, Cadence and ARM are updating 55ULP, 40ULP and 28ULP TSMC process technologies. Together, the companies will integrate ARM Cortex processors, ARM CoreLink system IP and ARM Artisan physical IP along with RF/analogue/mixed-signal IP and embedded flash in the Virtuoso-VDI Mixed-Signal Open Access integrated flow for theTSMC process technology.

Cadence has revealed that TSMC has adopted the company's solutions for 16nm FinFET library characterisation. Based on Cadence Virtuoso Liberate characterisation solution and Spectre circuit simulator, the library characterisation tool setting includes environment setup and sample templates for TSMC standard cells.

A transistor-level EMIR solution, designated the Voltus-Fi Custom Power Integrity Solution, has been introduced by Cadence. Delivering foundry-certified, SPICE-level accuracy in power signoff, the solution aims to create the fastest path to design closure. Enabled by the company's Spectre Accelerated Parallel Simulator signoff SPICE simulation, the company claims that the solution provides best-in-class accuracy at the transistor level, thereby m...

Three additions to the Cadence OrCAD product line has been introduced, targeting the acceleration of the mainstream PCB design process and the boosting of productivity and efficiency. The OrCAD products include OrCAD Engineering Data Management (EDM), a comprehensive collaboration and management environment for OrCAD Capture; OrCAD Library Builder, a rapid automated part builder; and OrCAD Documentation Editor, an intelligent, automated PCB docum...

A prototyping tool which speeds time-to-market, has been introduced by Cadence. Protium is an expansion of the Cadence Palladium XP II suite. Built using Xilinx Virtex-7 2000T FPGAs, the prototyping tool provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimises FPGA bring-up steps, thereby speeding up time-to-market.

Following rigorous competitive evaluation, Ricoh implemented the Cadence Quantus QRC Extraction solution. Utilising it for all large-scale, complex digital designs and mixed signal power management ICs for their mobile products, this parasitic extraction solution enabled Ricoh to cut its design flow parasitic extraction time in half for SoC designs.

Delivering up to five times faster runtime for single and multi-corner extraction versus competing solutions, Cadence Design Systems has announced its next-generation tool for RC extraction. Quantus QRC Extraction solution accelerates design signoff and sets a new standard for performance with its massively parallel architecture.

Cadence Design Systems' Cadence Quantus QRC Extraction solution has been certified for TSMC 16nm FinFET. The solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.

Allowing for the analysis of over 50M cells flat in the design, the Cadence Tempus Timing Signoff Solution has been used by Hitachi for its latest giga-scale design. Hitachi also utilised Tempus Timing Signoff Optimization (TSO), which resulted in a reduction of overall closure time to just 3 weeks, down from almost 2 months.    

Cadence Design Systems, Inc announced that NextG-Com has completed its port of the ALPS520 LTE Layer 2 and 3 protocol to the Cadence Tensilica ConnX BSP3 processor core. This combined hardware/software solution can be used to speed the design of LTE modems for cellular phones, tablets and other end-user equipment.

Cadence Design Systems, Inc announced that QNX has ported its QNX Acoustics for Active Noise Control (ANC) software to the Cadence Tensilica HiFi Audio/Voice digital signal processing (DSP) core. The Tensilica HiFi Audio/Voice DSP from Cadence is available immediately. 

Cadence Design Systems has announced that a production proven host controller intellectual property (IP) for USB 3.0 has been added to the Cadence IP offering. The Cadence USB 3.0 xHCI host controller IP was originally developed by Fresco Logic, a global fabless semiconductor company that develops and markets advanced connectivity solutions.

Cadence Design Systems have announced that ON Semiconductor has adopted Virtuoso Layout Suite for Electrically Aware Design (EAD) for real-time electrical analysis of parasitic and electromigration impact on its custom physical design implementation flow. With Virtuoso Layout Suite EAD, ON Semiconductor circuit and layout designers will be able to significantly reduce design time and improve the energy efficiency of their designs by immediately s...

Cadence Design Systems Inc announced that its high-performance FastSPICE simulator, Spectre XPS (eXtensive Partitioning Simulator) now supports transistor-level mixed-signal design. Delivering up to 10X faster throughput versus previous advanced-SPICE solutions, Spectre XPS enables faster and more comprehensive simulation for large, complex designs including mixed-signal designs.