VLIW architectures have proven to be an optimal target for today’s C compiler technology. VLIW architectures do not require designs to sacrifice software development productivity for the very high-performance processing needed for the next-generation high-end video, multimedia and wireless
devices. Companies developing high-end video processing devices that implement the next generation H.264 or VC1 video standards and companies developing wireless baseband processing devices targeting the next generation WiMAX or LTE (next-generation W-CDMA) wireless standards can
benefit the most from the new capabilities in Processor Designer. With the software programmability available through the Processor Designer flow, users can make adjustments for late changes in the standards and provide devices that can be programmed for different standards. This can be done
while maintaining the performance of custom hardware.
If redundant parallel data paths are included, they make the design too expensive. Very specific customization of every application is required to be cost effective. The new enhancements to the LISA language, which are now available through CoWare Processor Designer, enable users to parameterize
the processor architecture with the number of parallel data paths (VLIW slots) to determine the optimal number of slots for a specific application and then customize each slot individually. The new Processor Designer fully automates the exploration of the number of parallel data paths by
generating software development tools such as assembler, linker, simulator,
and a highly-optimizing C complier for software performance measurement, as well as RTL code generation for hardware cost estimation. The result is that the user can script the exploration of various architectures with different data paths in a matter of hours rather than months.