Cadence has also made enhancements to the 7nm Custom Design Reference Flow and library characterisation flow. These design tool advancements have enabled Cadence to accelerate initial deliveries of its high-speed SerDes and low-latency DDR IP cores to leading customers, with test chips expected to tape out in the fourth quarter of this year.
These products represent the first of a comprehensive portfolio of application-optimised 7nm solutions to be developed by Cadence.