Power integrity is the discipline of providing clean power to the device under test (DUT) by minimizing noise on the Power Delivery Network (PDN). It quickly is becoming one of the biggest challenges in test interface design. By maintaining a low impedance path from tester to DUT across all operating frequencies of the device, a constant voltage can be provided to the DUT in a high di/dt environment. The main strategy used to accomplish this is minimizing the loop inductance from the DUT to the nearest bypass capacitors.
After providing an overview of power integrity, this presentation will describe how power integrity relates specifically to the test interface, beginning with the load board. Additionally, the presentation will describe the impact of the contactor. The contactor can significantly impact the ability of the PDN to provide clean power to the DUT. It is important to understand the contactor’s influence on the PDN. This presentation will discuss the variables that impact how and when the contactor impacts the PDN.