“We thank Cadence for this significant and timely contribution to Accellera,” said Shrenik Mehta, chair of Accellera. “We welcome this new technology aimed at strengthening our Verilog-AMS standard, which is critical for engineers tasked with conducting efficient, yet deep, verification on some of today’s most complex chips.”
“As the industry leader in mixed-signal design enablement, we are contributing this open-format wreal technology to enable the development of interoperable solutions to meet the needs of our industry,” said Sandeep Mehndiratta, solutions marketing group director at Cadence. “With the ability to conduct mixed-signal verification at digital speeds—even running nightly regression tests—we are confident verification teams will see significant benefits from deploying this technology.”