The new platform for emulation, prototyping and software development will include up to six high performance Virtex-6 FPGAs and will allow software development prior to ASSP silicon availability. ST-Ericsson deployed its first generation PEPS system, which included six Virtex-4 FPGAs, to develop its highly acclaimed U8500 Smartphone Platform.
The upcoming PEPS-2 system will allow customers to develop even larger and more complex ASSP platforms and run the system faster, with much lower power, due to the Virtex-6 FPGAs.