Fast start-up delay allows the detection of a voltage fault before the rest of the system powers up providing maximum safety in hazardous start-up fault conditions. Low Power-on-Reset (VPOR) prevents false resets, premature enable or turn-on of next device, and proper transistor control during power-up and power-down.
Reset output signal is asserted when the voltage at VDD drops below the negative voltage threshold (VIT-) or when manual reset (MR) is pulled to a low logic (VMR_L). Reset signal is cleared when VDD rise above VIT- plus hysteresis (VIT+) and manual reset is floating or above VMR_H and the reset time delay (tD) expires.
Reset time delay can be programmed by connecting a capacitor between CT pin and ground. For a fast reset CT pin can be left floating.
Additional features include; built-in glitch immunity protection for MR and VDD, built-in hysteresis, low open-drain output leakage current (ILKG(OD)).
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