Reset output signal is asserted when the voltage at VDD drops below the negative voltage threshold (VIT-) or when manual reset is pulled to a low logic (VMR_L). Reset signal is cleared when VDD rise above VIT- plus hysteresis (VIT+) and manual reset (MR) is floating or above VMR_H and the reset time delay (tD) expires. Reset time delay can be programmed by connecting a capacitor between CT pin and ground. For a fast reset CT pin can be left floating.
Additional features include, low power-on reset voltage (VPOR), built-in glitch immunity protection for MR and VDD, built-in hysteresis, low open-drain output leakage current (ILKG(OD)). TPS3840 is a voltage monitoring solution for industrial applications and battery-powered / low power applications.
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