Low power memory compiler programme opened for 30 days

22nd January 2020
Lanna Deamer


SureCore is opening its low power memory compiler for 30 days to qualifying companies to evaluate the capabilities of its PowerMiser and EverOn standard SRAM IP products on low power metrics. The new service will prove particularly useful for constraint and compute intensive SoC designs.

The Compiler Access Programme (CAP) is the newest service for the company's low power SRAM IP that are implemented in CMOS and SOI processes for demanding imaging, artificial intelligence, IoT, medical and wearable applications.

CAP is available to SoC designers to evaluate the performance and low power capabilities of SureCore's low power SRAM on 22nm, 28nm or 40nm process technology. Companies can apply for CAP here.

"AI, imaging, IoT, medical and wearable devices all require enhanced power profiles. With SRAM integration levels continuing to rise, our standard products help deliver the power savings needed in these competitive market spaces. Through CAP, we're opening a low power memory test drive to optimise power budgets and manufacturability," explained Paul Wells, sureCore's CEO.

Companies qualifying for CAP receive a link and password plus the Compiler User Guide. Designers can then explore optimal performance/lowest power SRAM that meets project requirements.

CAP will generate datasheets that cover detailed PPA information, including access times, dynamic power, and sleep/deep sleep/standby leakage power, based on the requested instances and operating environment.

PowerMiser and EverOn

PowerMiser and EverOn Low-Power SRAM IP are both silicon-proven, process independent, variability tolerant and features dynamic and static power consumption, with EverOn delivering low voltage operation.

PowerMiser delivers static and dynamic power performance. Its patented 'Bit Line Voltage Control' techniques have the added benefit of virtually eliminating performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are offered.

The PowerMiser compilers support capacities up to 576Kbit with word lengths up to 144bits with three multiplexing factors; 4, 8 and 16. The compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.

EverOn operates down to 0.6V across process, voltage and temperature delivering an operating voltage range from 0.6-1.21V. It provides an unprecedented 20MHz cycle time at 0.6V scaling to over 300MHz at 1.21V, opening new capabilities for wearable and Internet of Things applications.

The EverOn Ultra-Low Voltage compiler supports synchronous single port SRAM with operating voltages ranging from 0.6-1.21V and memory capacities ranging from 8Kbytes to 576Kbytes with maximum word lengths of 72bits.

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