DRP-accelerated image processing with MPUs
The Dynamically Reconfigurable Processor (DRP) is runtime-reconfigurable hardware that combines the flexibility and expansion capability of a software programmable CPU with the performance and efficiency of dedicated IP.
Pairing a DRP with an Arm Cortex-A9 core and 4 MB of on-chip RAM, the Renesas RZ/A2M microprocessor enables a new, hybrid approach to image processing.
Designers can create machine vision applications that satisfy the size, power, and cost constraints of embedded systems, supported by a flexible methodology for the rapid time to market and iterative product feature enhancements required for competitive products.
For more information, watch the video below.
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