Innovative Silicon To Present Floating Body Memory Array Results At ISSCC
Innovative Silicon, Inc. (ISi), developer of the Z-RAM zero-capacitor floating body memory technology has announced the upcoming delivery of a presentation titled “A 2ns-Read-Latency 4MB Embedded Floating Body Memory Macro in 45nm SOI Technology” in collaboration with AMD at the International Solid State Circuits Conference (ISSCC).The
ISi’s Anant Singh will present the paper, which was also written with the assistance of: Philippe Bauser, Paul de Champs, Hamid Daghighian, Dave Fisch, Philippe Graber and Michel Bron of ISi, and Michael Ciraula, Don Weiss, and John Wuu from AMD. The paper describes an embedded memory macro developed for high-performance microprocessors using a single-transistor floating-body cell. Eight 4Mb macros were incorporated on a test chip fabricated in a 45nm SOI logic process. Silicon measurements confirmed a 2ns read latency with a memory-macro operating window of 0.6V.