Innovative Silicon To Present Floating Body Memory Array Results At ISSCC

4th February 2009
ES Admin
Innovative Silicon, Inc. (ISi), developer of the Z-RAM zero-capacitor floating body memory technology has announced the upcoming delivery of a presentation titled “A 2ns-Read-Latency 4MB Embedded Floating Body Memory Macro in 45nm SOI Technology” in collaboration with AMD at the International Solid State Circuits Conference (ISSCC).
The findings, highlighted in a co-authored paper, result from collaborative efforts between the two companies over the past three years to bring-up Z-RAM memory on a contemporary SOI process technology. Unlike ISi’s focus on developing Z-RAM memory as a stand-alone DRAM replacement, this paper will demonstrate Z-RAM memory implemented as an ultra-dense, multi-megabit, on-chip cache memory which occupies approximately 60 percent less area than conventional cache memories. The presented results demonstrate the fastest floating-body memory array reported, and the most advanced technology node reported.

ISi’s Anant Singh will present the paper, which was also written with the assistance of: Philippe Bauser, Paul de Champs, Hamid Daghighian, Dave Fisch, Philippe Graber and Michel Bron of ISi, and Michael Ciraula, Don Weiss, and John Wuu from AMD. The paper describes an embedded memory macro developed for high-performance microprocessors using a single-transistor floating-body cell. Eight 4Mb macros were incorporated on a test chip fabricated in a 45nm SOI logic process. Silicon measurements confirmed a 2ns read latency with a memory-macro operating window of 0.6V.

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