Memory

How pseudo-SLC mode can make 3D NAND flash more reliable

10th March 2020
Alex Lynn

The data that computers across numerous sectors are collecting and processing needs to be stored, a demand that continues to push storage costs higher. Cost is a pain point in the consumer electronics sector, and manufacturers of smartphones and laptops want to see storage costs decrease. However, that decrease can’t come at the expense of the safety and reliability that both commercial and industrial enterprise servers require. 

One answer to this dilemma is the potential for lowering data storage costs which increased storage density presents. Greater storage density, for example, in solid-state drives (SSDs), SD-cards, and USB drives could help cut costs.

An increase in data storage density can be achieved by reducing the size of the transistors used and stacking the transistors vertically. In addition, data storage density can be enhanced by increasing the number of bits stored in each cell. 

The continued scaling of semiconductor manufacturing technology is making it possible to fit more memory cells on a chip for the same price. But with limits to how far this scaling can go, manufacturers of flash memory drives are seeking new ways to reduce per-bit costs while also expanding storage density. 

Nonvolatile NAND flash memory, unlike DRAM memory, retains data even when the power is off, so it’s an ideal fit for portable device storage requirements. NAND flash memory has become an increasingly important storage technology in products such as SSDs, SD-Cards, and USB drives. 

A single-level cell (SLC) NAND flash drive stores one bit per cell. Multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC) NAND flash drives store two, three, and four bits per cell, respectively. 

Housing more bits in a cell causes the cost of storage to shrink on a per-bit basis. However this cost decrease is accompanied by slower processing. The slower processing occurs because storing multiple bits in a single cell calls for higher precision during the write and readout process. Boasting more capacity than SLC NAND flash drives, MLC, TLC, and QLC NAND flash memory nevertheless operate more slowly than SLC flash. SLC flash drives aren’t slowed down by requirements for more precise control of thresholds and programming voltages. The number of times each cell can be erased and reprogrammed, i.e., the cell’s write endurance, is also much lower with MLC, TLC, and QLC NAND flash than with SLC NAND flash. 

Often-overlooked, pseudo-single level cell (pSLC) technology combines the best qualities of both single-level and multi-level technologies. 

On the one hand, pSLC takes its cue from MLC, TLC, and QLC technologies, which employ modern scaling processes to achieve higher transistor and cell density. On the other hand, instead of multiple bits per cell, pSLC reduces the storage to one bit per cell. By reverting to having just one bit, pSLC flash can operate faster and more reliably than in its native mode. Storing a single bit per cell also increases the write endurance by up to 20 times. 

As a result, pSLC can achieve the performance, reliability, and life span of SLC NAND flash while benefiting from cost savings that MLC, TLC, and QLC NAND flash technologies make possible. Bridging the gap that has stretched between SLC benefits on the one side and the attractive cost the newer technologies offer on the other, pSLC improves the performance, reliability, and endurance of MLC, TLC, and QLC NAND flash. Even though pSLC reduces the capacity of MLC, TLC, and QLC by 50%, 66.6%, and 75%, respectively, the cost per bit is lower than with SLC because of the higher cell density. 

Not all flash memory devices can support pSLC mode, but many do. Successfully implementing pSLC mode requires a high-quality controller, with firmware optimised for the specific flash memory used, to provide the highest performance, most secure data storage. 

Hyperstone, a fabless semiconductor and NAND flash controller design company, has designed flash controllers to support the pSLC mode which provide the users with the optimised speed performance, write cycles, and cost. This gives manufacturers greater design flexibility without sacrificing performance or reliability in the NAND applications.

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