Reducing Switching Power with Intelligent Clock Gating
Xilinx introduces the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30 percent for Virtex®-6 and Spartan®-6 FPGA designs
Partial Reconfiguration of Virtex FPGAs in ISE 12
Reducing Switching Power with Intelligent Clock Gating
Whitepaper - Anti-Tamper Memory