This iPDK enables full support of the Custom Compiler visually-assisted layout flow, including groundbreaking features that reduce the time it takes for users to layout and connect FinFET devices.
The Custom Compiler solution integrates with Synopsys circuit simulation, physical verification and digital implementation tools to provide UMC 14-nm process users with a complete custom design solution. “We have a long history of working with Synopsys to provide iPDKs for our customers,” said T.H. Lin, director of the IP Development and Design Support division at UMC.
“This new 14-nanometer iPDK enables layout designers, including our own internal team, to use Synopsys’ custom design tools for FinFET layout productivity. We are pleased to offer this resource to help customers streamline their design-in process on our volume-production 14-nanometer technology.”
“FinFET process technology is becoming very popular with our customers, but FinFET layout can be a challenge,” said Bijan Kiani, vice president of product marketing at Synopsys. “We collaborated with UMC to enable Custom Compiler for their 14-nanometer process, so UMC customers can use Custom Compiler’s visually-assisted layout to improve FinFET layout productivity.”
The 14-nm and other process iPDKs for Synopsys Laker and Custom Compiler design tools are available on request from UMC.