System-level performance optimisation capabilities for MIPS users

8th March 2016
Jordan Mulcare

UltraSoC has announced it is providing the benefits of its performance optimisation and system level profiling solutions to SoC development teams utilising Imagination Technologies’ MIPS processor architecture. This gives SoC designers access to a development environment that offers a holistic view of their entire system, encompassing not only MIPS processors via an interface between Imagination’s Codescape Debugger and on-chip UltraSoC blocks, but also CPUs and IP from other vendors, as well as custom logic, memory and bus structures.

MIPS is one of the most widely supported and deployed processor architectures. Its simple, streamlined and highly scalable RISC architecture delivers the highest performance per square millimetre of any licensable IP core, as well as high levels of power efficiency. By adding support for MIPS to its range of on-chip monitoring and analytics, UltraSoC complements the existing broad infrastructure of standard tools, software and services already available for the MIPS architecture.

“Designers are increasingly challenged to understand the system-level consequences of using multiple, heterogeneous CPU cores in conjunction with their own custom logic blocks, all running millions of lines of code,” said Jim Feldhan, President, SemiCo Research. “MIPS already has a strong development ecosystem: UltraSoC complements this perfectly, speeding development, increasing quality and cutting costs by allowing engineers to optimise performance and help address hard-to-spot bugs like deadlocks.”

“The UltraSoC tools can help engineering teams with MIPS CPUs in their systems better understand what is happening inside their SoCs for more efficient overall development,” said Jim Nicholas, Vice President of MIPS business operations, at Imagination. “With many markets now demanding the capabilities of heterogeneous multicore SoCs, designers need system-level solutions for performance profiling and optimisation. We welcome UltraSoC as yet another member of the vibrant ecosystem around MIPS CPUs.”

Rupert Baines, CEO, UltraSoC, commented: “MIPS is a key player in today’s SoC landscape. It is the leading CPU architecture in home entertainment products; it leads the field in network gateway and router applications; and in mobile it is one of only three CPU architectures supported by Android. We’re hugely excited to be working together with Imagination, one of the best-known names in the semiconductor industry, and we are already working with a joint customer who is using this solution in their production silicon.”

The development will enable whole-system analysis as well as supporting the classic processor debug and trace capabilities offered by MIPS IP cores. It provides an interface between Imagination’s Codescape Debugger and on-chip UltraSoC blocks, including a Processor Advance Module optimised for use with MIPS CPUs. The system will allow control and monitoring of heterogeneous multicore systems that include MIPS processors, providing the engineer with a holistic, system-level view of the real world operation of their SoC design, via Codescape, an ECLIPSE IDE or via third-party tools.

UltraSoC provides a toolbox of silicon IP that system architects and development teams can use to monitor and analyse the internal behavior of a chip – under real operating conditions and at 'wire speed'. These capabilities are valuable in the development phase of the device, allowing the engineering team to understand the often complex interactions between diverse on-chip processor blocks, custom logic and system software. The same features can also be employed when the chip is deployed in an end product, spotting unexpected behavior and providing hardware-based protection against malicious attacks and malfunctions.

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