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Synopsys HSPICE Precision Parallel technology delivers up to 7X speed-up for analogue/mixed-signal designs

20th September 2010

Synopsys Inc

ES Admin

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Synopsys unveiled new HSPICE(r) Precision Parallel (HPP) multi-threading technology that delivers up to 7X simulation speed-up for complex analogue and mixed-signal designs. In addition to the new HPP technology, the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analogue analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex circuits such as phase-locked loops, SERDES, data converters, high-precision custom digital and power management. With HSPICE 2010, design teams can accelerate verification of their analogue circuits across process variation corners and reduce the risk of silicon respins.

“We rely on HSPICE to simulate our analogue designs with sophisticated digital control logic functions,” said Xiaowei Wang, director of analog design at HiSilicon. “Using the latest HSPICE Precision Parallel technology on a data converter, we obtained a 7X speed-up on eight cores, reducing a multiple-day simulation to about 8 hours. HPP enables our analogue engineers to improve productivity by simulating multiple iterations of the designs in a single day.”

HSPICE Precision Parallel Technology

In 2008, HSPICE was one of the first commercial circuit simulators to introduce full multi-threading capability. The new HPP technology takes multi-threading performance to a new level for complex analogue circuits with significantly faster speed and class-leading multicore scalability. HPP combines an adaptive sub-matrix technology with optimised cache utilisation and streamlined device model evaluation to obtain fast, highly-scalable performance on today’s multicore machines. Efficient memory management allows simulation of post-layout circuits larger than 10 million elements.

“We evaluated HSPICE Precision Parallel technology to speed up our multimillion-element complex clock mesh network simulation,” said Antonio Todesco, SMTS design engineer, Graphics Silicon Engineering group at Advanced Micro Devices. “HSPICE Precision Parallel technology allowed us to achieve one-day turnaround time for ECO, extraction and simulation while using less memory and delivered the timing resolution needed to support clock mesh circuit integrity.”

“With the increasing use of digitally-assisted analogue circuits in SoCs, designers are demanding innovation in circuit simulation to significantly speed up transient simulation and to take advantage of the latest multicore compute resources,” said Paul Lo, senior vice president and general manager, Synopsys Analogue and Mixed-Signal Group. “We continue to invest in new HSPICE technology to improve simulation productivity for the HSPICE user community.”