Cadence Announces Updated Design and Verification IP for DDR PHY Interface

The DFI interface standard was developed through the collaborative effort of leaders in the semiconductor and EDA markets and has become the de facto industry standard for high-bandwidth memory interfaces.



“As the performance of the processors used in today’s consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SoC designers a way to easily incorporate high-performance memory into their SoCs,” said Marc Greenberg, director of marketing, SoC Realization, Cadence.



“Through our close working relationship with the DFI Group, we are able to offer our customers design and verification IP that supports the latest version of this popular interface standard.”



Cadence has over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface.



With the addition of support for LPDDR3 memory, the DFI standard can now be used in the development of SoCs targeting smartphone and tablet applications that require higher-bandwidth memory. The standard has been recognized by JEDEC, the microelectronics industry’s open standards organization.