Design

Cadence launches Incisive Debug Analyzer to reduce debug time and effort

10th October 2012
ES Admin
0
Cadence have launched the Incisive Debug Analyzer, a new and innovative verification debug product for RTL, testbench and SoC verification that offers significant reductions in debug time and effort. Cadence customers who have used this unique, multi-language debug solution have reported average time savings of up to 40 percent or more.
“Incisive Debug Analyzer is an innovative debug technology that has helped us fix bugs in minutes that previously would have taken hours to debug, including the root cause of complex multithreaded behaviors in our HDL design and, more importantly, in the verification environment,” said Eli Zyss, vice president of Silicon Design at Altair Semiconductor. “We see many verification and design engineers leveraging the post-process playback debugger and the cause analysis capabilities in Incisive Debug Analyzer. It is a great debug productivity enhancer.”

With many SoC companies now spending over 50 percent of their overall verification effort in debug, Incisive Debug Analyzer targets this significant verification bottleneck with unique debug features. For instance, the debugger allows users to step forward or backward through their hardware verification language and hardware description language. Additionally, users can click directly on a line or variable to jump forward or backward through time to the point when the source code line was executed or a variable value changed, allowing them to pinpoint the bug.

Other unique features include integrated, interactive log file analysis capabilities with smart filtering and clickable messages that take users directly to the point of interest in either the source code or the waveform database. The debugger provides relevant debug investigation information that allows users to quickly and easily filter messages coming from any platform (HVL and HDL code) and explore the cause of the messages by providing causality relations and debugging leads.

“Our customers have been seeking a comprehensive RTL, testbench and SoC debug solution to cut through the bottleneck of verification debug,” said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence. “Incisive Debug Analyzer provides them with the capabilities, accuracy, flexibility and speed to isolate and fix their bugs in record time.”

The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. It is scheduled for release by year’s end.

Product Spotlight

Upcoming Events

View all events
Newsletter
Latest global electronics news
© Copyright 2024 Electronic Specifier