Design

Highly scalable timing signoff flow in the cloud

16th June 2020
Alex Lynn
0

Synopsys has announced that its collaboration with TSMC and Microsoft has delivered a highly scalable timing signoff flow for use in the cloud. This extensive, multi-month collaboration among the three industry partners speeds up the path to signoff next-generation systems-on-chips (SoCs).

The flow dramatically improves throughput using Synopsys PrimeTime static timing analysis and StarRC parasitic extraction on the Microsoft Azure platform.

"With increasing design complexity due to advanced process technologies, larger library size, and higher number of operating conditions to analyse, turnaround time for the design signoff has become critical," said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. "Utilising a cloud platform offers a great way to accelerate signoff significantly and will fundamentally influence silicon design. TSMC is the first foundry to collaborate with design ecosystem partners and cloud providers to enable design in the cloud.

“Working with Microsoft and Synopsys, our cloud alliance has demonstrated remarkable throughput improvement and scalability of timing signoff and offers a flexible, secure and efficient way for our mutual customers to accelerate time to market for their SoCs."

"At advanced nodes, reducing design time requires technology innovation across the infrastructure and toolchain due to high process complexity," said Mujtaba Hamid, Head of Product Management, Silicon, Electronics and Gaming at Microsoft Azure. "This collaboration provides key insights into tradeoffs involved between cost and performance for these signoff iterations, thus helping the customers make effective decisions for the design of their silicon products."

On a multi-million gate design using the TSMC N5 process, PrimeTime static timing analysis and StarRC extraction, timing signoff was performed on Microsoft Azure's latest Edsv4-series compute instances. PrimeTime DMSA and StarRC multi-corner extraction scale-out saw significant throughput gains by massively parallelising the runs over hundreds of machines. Additionally, scaling-in showed major cost savings by running multiple scenarios on a single machine.

"Working with leading-edge companies, we see the need for a high throughput of design tools and platforms to shorten time-to-market, whether they run the tools on-premise or in the cloud," added Jacob Avidan, Senior Vice President of Design Signoff in the Design Group at Synopsys. "With the industry-leading and TSMC-certified PrimeTime and StarRC solutions on Microsoft Azure, our customers can leverage the cloud to signoff their chips with significantly higher throughput while meeting their PPA targets with TSMC's latest advanced process technologies."

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