Highly scalable switch silicon family designed for data centres
Cadence Design Systems has announced that Innovium has adopted the Cadence Innovus Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centres. The size and complexity of the highly innovative Innovium designs require high capacity, fast and accurate design tools for advanced-node design implementation.
The Cadence Innovus Implementation System provides Innovium with the following benefits:
- Massively parallel architecture: Lets Innovium handle large design sizes with multi-threading on multi-core workstations and distributed processing over networks of computers.
- GigaPlace solver-based placement technology: Provides Innovium with a slack-driven, pin access-aware placer that improves electrical and physical design convergence at advanced nodes.
- Multi-threaded, layer-aware optimisation engine: Enables Innovium to reduce dynamic and leakage power with the engine’s timing- and power-driven capabilities. With the comprehensive power reduction techniques inside the Innovus Implementation System, Innovium reduced power consumption by the end of the implementation stage to within two percent of final signoff power.
- Core engine technologies: Offers Innovium access to innovative implementation technologies for FinFET process nodes such as IR-aware placement, clock skewing for power, continuous congestion monitoring and optimised routers for handling self-aligned double patterning, meeting Power, Performance and Area (PPA) goals.
“Our highly skilled engineering team is always pushing the limits of massive, advanced-node SoC designs, and the Cadence Innovus Implementation System enabled us to achieve our PPA goals and overall engineering productivity so we can deliver our innovative and high performance designs to market within aggressive timelines”, said Keith Ring, Vice President of Technology at Innovium.
The Innovus Implementation System is part of the broader Cadence digital and signoff suite, which provides customers with an integrated full flow, delivering a predictable path to design closure. It supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.