Design

Hardened floating-point DSP blocks are IEEE 754-compliant

23rd April 2014
Nat Bowers

Altera is industry's first programmable logic company to integrate hardened IEEE 754-compliant, floating-point operators in an FPGA, delivering unparallelled levels of DSP performance, designer productivity and logic efficiency. The hardened floating point DSP blocks are integrated in Altera’s 20nm Arria 10 FPGAs and SoCs, as well as 14nm Stratix 10 FPGAs and SoCs.

Integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, enable customers to use Altera’s FPGAs and SoCs to address an expanding range of computationally intensive applications, such as high-performance computing (HPC), radar, scientific and medical imaging.

The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s innovative variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, Altera’s resource efficient, hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. This game-changing technology enables Altera to deliver up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices. DSP designers are able to choose either fixed or floating-point modes and the floating point blocks are backwards compatible with existing designs.

FPGAs feature a fine-grained, highly pipelined architecture that make them ideally suited for use as high-performance compute accelerators. The inclusion of hardened floating-point DSP blocks enable customers to use Altera FPGAs to address the world’s most complex HPC problems in big data analytics, seismic modeling for oil and gas industries and financial simulations. Across these and many other computationally intensive applications, FPGAs deliver the highest performance per Watt when compared to DSPs, CPUs and GPUs.

The integration of hardened floating-point DSP blocks in Altera FPGAs and SoCs can reduce development time by upwards of 12 months. Designers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point. As a result, timing closure and verification times are dramatically slashed. Altera also provides multiple tool flows that allow hardware designers, model-based designers and software programmers to easily target the high-performance floating-point DSP blocks in its devices.

Alex Grbic, Director of Software, IP and DSP Marketing, Altera, commented: “The implementation of IEEE 754-compliant floating-point DSP blocks in our devices is truly a game-changer for FPGAs. With hardened floating point, Altera FPGAs and SoCs offer a performance and power efficiency advantage over microprocessors and GPUs in an expanded range of applications.”

Altera 20nm Arria 10 FPGAs with hardened floating-point DSP blocks are available now. Floating-point design flows, including demonstrations and benchmarks, that target the hardened floating-point DSP blocks in Arria 10 devices will be available in the second half of 2014. Customers can start designing today with Arria 10 FPGAs using soft implementations of floating point and then seamlessly migrate to hardened floating point implementation when the design flows are available.

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