AVIX fully exploits the extremely powerful interrupt architecture of the PIC24 and dsPIC© microcontrollers. AVIX accomplishes this by never disabling interrupts meaning it does not increase the interrupt latency as defined by the controller’s hardware. Still communication between interrupt handling code and the main part of the application is offered and nested interrupt handling is preserved. Doing so, AVIX deserves the title “Zero Latency Interrupt RTOS”.
Also AVIX offers a mechanism called “Thread Activation Tracing”. This mechanism gives unprecedented insight in the activation of threads running under control of AVIX. Using a logic analyser, AVIX offers the possibility to ‘see’ online and real time when threads are active turning the black box of RTOS based system development white.
Of course AVIX offers all mechanisms one may expect from a professional RTOS like threads, mutexes, semaphores and so on.
As of today, AVIX is available in three different distributions so it can be fitted to the developers’ application in the most economic way.