Ethertronics reduces design schedule by half

This reduced the design schedule by 50% while also achieving more than 60% mask cost savings. The solution enabled Ethertronics to use automated Engineering Change Orders (ECOs) to deliver its complex product to market with the flexibility of a FPGA design. Ethertronics used Conformal ECO Designer in an unprecedented, innovative way that allowed them to do a complete rewrite of the Register-Transfer Level (RTL) code quickly and effectively.

Ordinarily, a standard metal-only ECO implementation flow requires having spare gates in the layout, but with this particular design, Conformal ECO Designer recycled and reconnected many of the existing gates in the netlist to implement the ECO function successfully. The design was processed on the backend and was ready for production in less than a day.

“It’s critically important for us to be able to respond quickly to frequent and unforeseen customer requirement changes. Conformal ECO Designer enabled us to modify our RF/mixed-signalproduct quickly and deliver it on time,” said Claudio Anzil, VP of Semiconductor Operations, Ethertronics. “Once the solution was in place, we rapidly created the new design without base layer changes. This also allowed us to implement the change on wafers, staged in manufacturing, eliminating more than half of the prototyping cycle time and cost. Conformal ECO Designer from Cadence will continue to be a valuable tool in our flow, especially as we transition to more complex products and more advanced process nodes.”

Conformal ECO Designer enables the implementation of RTL ECOs for pre- and post-mask layout and offers early ECO prototyping capabilities for driving critical project decisions. The solution is complemented by the industry’s most trusted equivalency checking for independent verification—the Conformal Logic Equivalency Checker—to deliver a complete verifiable solution.