Design

Arteris, EVE Strengthen Partnership to Provide Enhanced Design Flow for Mobile, Wireless SoCs

14th March 2011
ES Admin
0
Arteris Inc. and EVE today announced an integrated solution enabling system-on-chip (SoC) developers to easily generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform.
This integration allows SoC developers to create and ship their products sooner.
Arteris and EVE have worked together to integrate NoC interconnect creation and deployment with hardware emulation. The design flow allows the interconnect IP for the complete SoC to be assembled in Arteris FlexNoC, where the RTL is generated for input into the EVE Zebu emulation platform. This flow greatly simplifies architectural exploration and testing, allowing multiple test iterations in a single day using the actual applications that will be run on the final SoC.

This integration work was funded by the European Community in the framework of the FEDER project, where Ecole Nationale Superieure de Techniques Avancees (ENSTA ParisTech), a French institute for engineering education and scientific research, is also a partner.

“The Arteris-EVE integration allows us to easily test the impact of different cache sizes and the number of computing cores on metrics like latency and bandwidth,” said Dr. Woo-hyun Paik, vice president and research fellow of the DIS Group, LG Electronics. “We are able to quickly iterate tests on EVE Zebu while using the exact same NoC interconnect we will use on the finished silicon SoC.”
Dr. Luc Burgun, EVE’s chief executive officer and president, said, “This integration will benefit all our common customers, especially for mobile and wireless SoCs where Arteris FlexNoC is the best sustainable interconnect solution for connecting IPs and where we expect to see lots of changes in terms of design architecture.”

“The Arteris-EVE partnership has opened new directions for architectural analysis because only fast emulation provides the horsepower required to accurately validate multiple design architectures per day,” said K. Charles Janac, president and CEO of Arteris. “This approach perfectly fits our strategy to enable our SoC customers to make the most efficient use of silicon area and power as well as optimize software performance based on actual data traffic information.”

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