Andes Technology Adopts Cadence Digital Front-End Low-Power Flow

“Providing low-power products is essential to any company determined to be a serious competitor in embedded system applications,” said James Lai, associate vice president of Andes. “Teaming with Cadence, we were able to shorten the development cycles for our SoC platform IP products implementing the AndesCool™ low-power management feature, built on top of the CPF design and verification flows. By integrating CPF into our AndesCool framework, we are now getting ready to provide our customers a robust and flexible reference solution to help them hit their low-power targets efficiently and consistently.”

The Cadence approach to low-power design is based on a single, consistent notion of power intent that is pervasive through design, verification and analysis, and is production proven with hundreds of advanced low-power tapeouts. The Cadence CPF flow provides Andes an efficient path to initiate the development of its AndesCool low-power management framework. The flow provides an integrated power-intent specification throughout the entire ASIC design flow that has helped shorten Andes’ development cycle dramatically by removing replicated integration and verification efforts throughout the development stages. It also has saved Andes time by reducing design respins caused by the lack of power intent specifications in the old methodology.

The Cadence technology adopted by Andes includes Encounter RTL Compiler, Encounter® Conformal® Low Power and Incisive® Enterprise Simulator.

“Andes’ adoption of the Cadence low-power flow not only helped the company achieve its aggressive power goals for its SoC platform IP, but will enable Andes to help its customers enhance development effectiveness, too,” said Pete Hardee, product marketing director at Cadence. “Andes’ approach is a great example of living the EDA360 vision as companies turn to solutions that pan Silicon, SoC and System Realization to gain a competitive edge.”