Accelerating design delivery

The Cadence 14nm FinFET reference flow has been validated by Samsung using a quad-core design with the ARM Cortex-A53 processor, which was implemented with the low power methodology covering power gating, IEEE 1801 UPF2.0 power intent, memory retention and multi-bit-FF optimisation.

The Cadence digital and sign-off tools met all of Samsung’s accuracy requirements, providing customers with a faster path to implementation and closure, as well as optimal power, performance and area (PPA) on the 14LPP process. In addition, the Cadence sign-off tools have been certified for tapeout against the Samsung certification criteria. The tools in the flow include:

• Innovus Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 14nm design requirements, such as floor planning, placement and routing with integrated colour/pin-access /variability aware timing closure, and clock tree and power optimisation.
• Genus Synthesis Solution: Delivers improved productivity during register transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation.
• Quantus QRC Extraction Solution: Offers best in class accuracy versus foundry baseline, multi-patterning, multi-colouring, and a built-in 3D extraction capability.
• Conformal Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels.
• Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low power equivalence checking with structural and functional checks to allow full chip verification of power efficient designs.
• Tempus Timing Signoff Solution: Provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation.
• Voltus IC Power Integrity Solution: Cell level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full chip system-on-chip (SoC) power sign-off accuracy.
• Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage dependent checks, pattern matching and in-design sign-off.
• Litho Physical Analyzer: Enables designers to detect and repair process hotspots to improve design manufacturability and yield of digital, custom and mixed signal designs, libraries and IP.
• Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation.
• Modus Test Solution: Provides scan and logic/memory built-in self test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimise production test cost.

“Samsung worked closely with Cadence to put a certified reference flow in place so our joint customers can reduce iterations and improve predictability when creating 14nm FinFET designs,” said Ben Suh, Senior Vice President of Sales and Marketing at Samsung Foundry. “The ease of use of the design flow and methodology enhances the value of our foundry capability and provides our customers with the ability to create high value designs within tight market windows.”

“The certification of the Cadence tools ensures tight correlation and predictability, providing customers with confidence that 14nm FinFET designs work as intended,” said Dr Anirudh Devgan, Senior Vice President and General Manager of the Digital and Signoff Group and the System Verification Group at Cadence. “Customers using the Cadence flow on the Samsung 14nm FinFET process can also achieve smaller area, higher performance and lower power-consumption benefits in addition to faster turnaround times.”