Design
Lattice and Beyond Semiconductor to Collaborate in Processor Compiler Tools Development
Lattice Semiconductor today announced it will collaborate with Beyond Semiconductor in the development of compiler tools for Lattice's soft processors. The collaboration will include updates and performance improvements for Lattice's embedded processor IP compilers and development tools.
Lattice FPGA Design Tool Suite Includes Advanced Support for High Performance DDR Interfaces
Lattice Semiconductor has announced Version 8.0 of its ispLEVER FPGA design tool suite, which includes many enhancements for the design of high speed double data rate (DDR) interfaces for the LatticeECP3 FPGA family. These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.
Lattice Updates Software Design Tools for Hot Swap Control and Power Management
Lattice Semiconductor Corporation has announced Version 5.2 of its PAC-Designer mixed signal design tool suite with new device support and productivity features. The PAC-Designer 5.2 software now supports two new higher performance Power Manager II products: the ispPAC®-POWR1014-2 and ispPAC-POWR1014A-2 devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap control, voltage rail supervision and power supply sequencing ICs. PAC-Desi...
Maplesoft’s new engineering products provide tools to enhance understanding and tackle complexity of modern engineering
Maplesoft has announced several new products that will help educators, researchers and students better understand and manage the complexity of engineering modelling and simulation problems. Available from Adept Scientific, MapleSim, the most advanced solution for physical modelling, combined with a collection of new toolboxes, enables fast model development, advanced analysis and the creation of complex multi-domain models that lie at the core of...
Altera Continues Its 2X to 3X Compile Time Advantage with Quartus II Software Version 9.1
Altera Corporation today announced the release of Quartus® II software version 9.1, the industry's number-one software in performance and productivity for CPLD, FPGA and HardCopy® ASIC designs. New features and enhancements within Quartus II software v9.1 reduce compile times 20 percent versus the previous software release, while continuing to deliver on average 2X to 3X faster compile times compared to competing high-density 40-nm and 65...
Zuken Announces Free Webinars
In the area of System Design, System Engineers have accomplished their design tasks using an array of different tools including spreadsheets, diagramming programs and dumb graphics. Integration between block diagrams and interconnect and system wiring diagrams has typically involved manual operations resulting in significant time and cost burdens.
Synopsys chosen by Realtek as its primary EDA partner
Synopsys has announced that Realtek Semiconductor Corp, a leading provider of advanced IC products for communications network, computer peripheral and multimedia applications, has signed an expanded business agreement establishing Synopsys as its primary EDA partner. Under the new multi-year agreement, Realtek has extended its use of Synopsys’ Galaxy Implementation, Discovery Verification and Confirma Rapid Prototyping Platforms, as well as Syn...
Synopsys TetraMAX ATPG cuts test development schedule at Arrow Electronics
Synopsys has announced that Arrow Electronics successfully deployed Synopsys’ TetraMAX automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high quality manufacturing tests. Stringent quality goals combined with increasing design complexity stimulated the need to improve ATPG performance at Arrow. By utilising TetraMAX ATPG’s multicore processing capability on their quad-core ...
EDA Solutions announces Tanner process design kit support for X-FAB's 0.18µm technologies
EDA Solutions announces that X-FAB has released two 0.18µm process design kits for Tanner Tools Pro on X-TIC, X-FAB's online technical database. Tanner Tools Pro is the software suite for the design, layout and verification of analog, mixed-signal (A/MS), RF and MEMS ICs from Tanner EDA, the world leader in PC-based A/MS and MEMS circuit design software. The release of this new kit extends X-FAB's PDK support for Tanner tools, adding X-FAB's 0.1...
Strategic relationship with SiliconAid extends ASSET’s ScanWorks platform into chip test and verification
ASSET InterTech and SiliconAid Solutions have formed a strategic relationship whereby ASSET will integrate its first integrated circuit (IC) test tool into the ScanWorks platform for embedded instrumentation and resell SiliconAid’s insertion and verification tools that support the emerging IEEE P1687 Internal JTAG (IJTAG) standard. SiliconAid is a supplier of world class chip verification and debug tools that support the IEEE 1149.1 Boundary-S...