Design
ProximusDA teams with STMicroelectronics to Develop Next-generation Distributed SOC TLM Virtual Prototypes
ProximusDA today announced its joint efforts with STMicroelectronics to develop the next generation of software virtual prototypes. The collaboration combines ProximusDA’s expertise in parallel code distribution with STMicroelectronics’ deep knowledge of Transaction Level Modeling and advanced distributed-computing architecture.
Supermicro Announces X10 Server Building Blocks Supporting Intel Haswell Processors
Super Micro Computer today announced new X10 Motherboard and Server Building Block Solutions that support Intel’s highly anticipated future Xeon processor E3-1200 V3 and 4th Generation Intel Core processor families.
Mentor Graphics and GLOBALFOUNDRIES Deliver 20nm Design Kits for Advanced Design Enablement
Mentor Graphics announced it has collaborated with GLOBALFOUNDRIES to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform. The design kit enables mutual customers to achieve the best performance, power and area with faster design closure times.
CaetanoBus Streamlines its Electrical Design Processes Using Capital Software from Mentor Graphics
Mentor Graphics and CaetanoBus today announced successful application of the company’s Capital software suite to the development of CaetanoBus’ flagship C5 coach. The C5 coach offers a wide range of configuration options and includes innovative electrical/electronic systems that significantly boost efficiency, safety, and reliability
LDRA–Lauterbach integration delivers complete code coverage, test case verification and certification compliance for broad range of applications and platforms
LDRA has integrated the LDRA tool suite with the Lauterbach TRACE32 Debugger and Simulator. Lauterbach’s hardware-assisted debug tools ease the interface to the embedded device, enabling developers to download and fully test an application on the target.
Cadence Design Tools Certified for TSMC 16nm FinFET Process and for TSMC 20nm Process
Cadence Design Systems announced today that several of its system-on-chip development tools have achieved version 0.1 of design rule manual and SPICE model tool certification for TSMC’s 16-nanometer FinFET process.
Agilent Technologies Introduces Electrical Retimer Solution to Solve Key Challenges in Designing Chip-to-Chip Links
Agilent Technologies is pleased to introduce today the latest addition to its repeater model library for quickly and accurately solving the challenge posed by signal distortion in the multigigabit-per-second regime. The retimer solution, available in the Advanced Design System 2013 Transient Convolution Element and SystemVue 2013 AMI Modeling Kit, is used for designing electrical retimers in chip-to-chip, high-speed digital links.
AdaCore Announces Successful Completion of Project Hi-Lite
AdaCore and its research partners today announced the successful completion of Project Hi-Lite, a three-year, €3.9 million effort aimed at popularising formal methods in the development of high integrity software by combining formal verification and testing.
TSMC Certifies Synopsys' Digital and Custom Solutions for 16-nm FinFET Process
Synopsys announced that TSMC has certified a comprehensive list of custom and digital design tools from Synopsys for 16-nm FinFET process Design Rule Manual and SPICE V0.1. TSMC's certification is built on early collaboration for extraction and modeling of 3-D parasitics in FinFET devices and extends to full-line design implementation solutions.
Agilent Technologies' Newest 3-D Electromagnetic Simulation Software Release Targets EMI Compliance
Agilent Technologies today announced the latest release of Electromagnetic Professional, its 3-D electromagnetic simulation software. EMPro 2013 helps design engineers identify and resolve difficult electromagnetic interference problems.