Design
Cadence Physical and Electrical DMF Signoff adopted by UMC
Cadence Design Systems reveal that after extensive benchmark testing, semiconductor foundry United Microelectronics Corporation has adopted the Cadence “in-design” and signoff design-for-manufacturing flows to perform physical signoff and electrical variability optimization for 28nm designs. The flows address both random and systematic yield issues, providing customers with another proven foundry flow for 28nm designs.
Hitachi utilize the Cadence Rapid Prototyping Platform
Cadence Design Systems reveal that Hitachi decreased development time and accelerated time to market for new IT products by utilizing the Cadence Rapid Prototyping Platform. Hitachi collaborated with Cadence as a strategic partner on an integrated verification and early software development environment to enhance quality and shorten turnaround time for Hitachi’s new IT products. Hitachi successfully implemented a system-level co-verification en...
Altium and Silicon Labs announce Design Content for EFM32 Gecko MCUs
Altium has released a new range of component libraries for board-level designs using the ARM Cortex-M based EFM32 Gecko microcontrollers, which were developed by Energy Micro (recently acquired by Silicon Labs). Available now from AltiumLive the solution delivers board-level component models and corresponding supply chain information, such as real-time price and availability data from distributors and vendors including Digi-Key, Arrow and Farnell...
XMOS' xTIMEcomposer Studio IDE makes developing Multicore code easy
XMOS has unveiled latest version of xTIMEcomposer Studio development suite for its xCORE multicore microcontrollers. The new integrated development environment includes everything required for embedded design in a single Eclipse-based environment including an editor, LLVM compiler, debugger, XTA static timing analyzer, simulator, xSCOPE real-time code instrumentation tool and flash burning tools.
Fujitsu's Regression Verification Time cut by Cadence Incisive Platform by 3X
Cadence unveil that Fujitsu has decreased the regression verification time for a system-on-chip design by 3X using the Incisive Enterprise Simulator and the Incisive Enterprise Manager. Part of the Cadence System Development Suite, the Incisive functional verification platform delivers unique verification management and automation capabilities that tackle the complexities of SoC verification.
A new version of DASYLab now available in the UK
DASYLab's updated version, the point-and-click data acquisition and control software from measX GmbH & Co is now available in the UK from Adept Scientific. DASYLab's function block interface makes it easy to set up and control measurement data applications in a standard PC Windows environment without programming; and new DASYLab 13 sees a significant upgrade in capability and flexibility by allowing users to define their own custom functions ...
CTU Prague Students Achieve Microwave and mm-Wave Circuit Design Success with AWR
The Czech Technical University in Prague challenges its graduate engineering students to master the basic design of microwave circuits and subsystems and become familiar with the concepts of active and passive microwave and millimeter wave circuit designs. CTU uses AWR’s Microwave Office circuit design software and AXIEM EM simulation software extensively in both coursework and research because it is fast to learn and easy to use, enabling stud...
Cadia Networks introduce Ultra-Compact, Ruggedized Embedded System
Cadia Networks unveil its newest Ultra-Compact, ruggedized embedded system into their family of products, the CES-1525. This Ultra-Compact system is packed with features and still offers room for expansion in a footprint about the size of a 3.5” hard drive. The CES-1525 is equipped with an Intel Atom D525 processor running at 1.8GHz, on-board soldered 2GB DDR3, dual Gigabit Ethernet ports, up to 4 COM ports, USB ports, and dual independent VGA ...
Synopsys Announces Complete 28-nm Data Converter IP Portfolio
Synopsys reveal availability of its 28-nanometer DesignWare data converter IP portfolio,which includes analog-to-digital converters, digital-to-analog converters and integrated PLLs. Implementing Synopsys' new data converter architecture in the 28-nm process node resulted in up to 76 percent reduction in power consumption and up to 86 percent reduction in area use, which reduces system costs for wireless networking and mobile communications syste...
QA•C++ upgraded by PRQA
PRQA | Programming Research unveil the upgrade QA•C++. Version 3.1, a new release of this leading static analysis tool for C++ environments that incorporates native 64-bit support for Windows, Linux and Solaris along with support for ISO C++ 2011. QA•C++ 3.1 offers full support of native 64-bit hardware environments to satisfy the growing demand from Windows, and in particular the UNIX-like community where 32-bit libraries are no longer being...