Communications

Interrupt handling in the Cortex-M

9th August 2012
ES Admin
0
The Cortex-M series processors include an interrupt controller called the Nested Vector Interrupt Controller for interrupt handling such as interrupt prioritisation and interrupt masking. The NVIC contains a number of programmable registers for interrupt management such as enable/disable, and priority levels.
These registers are memory mapped. A number of functions are provided in the Cortex Microcontroller Software Interface Standard compliant driver library from the microcontroller vendors to help the interrupt management easier.

The priority levels are defined by 8-bit width registers, but only the MSB bits are implemented. In the Cortex-M0 and Cortex-M0+ processors, there are four programmable priority levels. In the Cortex-M3 or Cortex-M4 processors, the number of priority levels can range from 8 to 256. There are two additional non programmable priority levels for NMI and a fault exception handler called HardFault.

Nested interrupts are automatically handled by the NVIC. Once the priority levels of each interrupt are programmed, the NVIC handles the interrupt prioritisation and masks out same or lower priority interrupts when an Interrupt Service Routine is running. If a higher priority interrupt takes place, it will pre-empt the running ISR to allow the higher priority ISR to be executed as soon as possible.

When an interrupt takes place, the processor will determine the start address of the ISR from a vector table automatically. By default the vector table is placed in the beginning of the memory space, but can be relocated to another address location by a bootloader or by user software. The vector table provides the initial value for the Main Stack Point and the reset vector address.

The interrupt latency of the Cortex-M series processor is quite low and is deterministic. For example, the Cortex-M3 and Cortex-M4 processors have an interrupt latency of only 12 clock cycles. This latency includes time required to push a number of registers to the stack, which allows an ISR to be written as a normal C function, and avoid any hidden software overhead in interrupt processing. Together with the vectored interrupt support, the interrupt features of the Cortex-M series processors are easy to use and provide outstanding interrupt handling capability at the same time.

If this abstract has piqued your interest, read the full article online in the August issue of Electronic Specifier Design, by clicking here.

Product Spotlight

Upcoming Events

View all events
Newsletter
Latest global electronics news
© Copyright 2024 Electronic Specifier