Silicon Labs has introduced a new family of low power PCI Express (PCIe) Gen 1/2/3/4 clock buffers that provide ultra-low jitter clock distribution in 1.5 and 1.8V applications. With additive jitter performance of 40fs RMS (typical), Silicon Labs’ new Si532xx PCIe clock buffers provide more than 90% margin to stringent PCIe Gen 3 and Gen 4 jitter specifications, simplifying clock distribution and de-risking product development.
Increasingly, data centre hardware designs including Network Interface Cards (NICs), PCIe bus expanders and High Performance Computing (HPC) accelerators are using low power 1.5 or 1.8V supplies to minimise overall power consumption.
Powered from a single 1.5-1.8V supply and featuring up to 12 clock outputs, the Si532xx buffers are ideally suited to provide low-jitter PCIe clock distribution in low power designs. The Si532xx clocks support PCIe Common Clock, Separate Reference No Spread (SRNS) and Separate Reference Independent Spread (SRIS) architectures, enabling them to be used in a wide variety of applications.
The Si532xx clocks are non-PLL-based fan out buffers, supporting the distribution of spread spectrum clock signals without impacting signal integrity. As the number of PCIe endpoints continues to expand in server and storage applications, system designers are tasked with buffering more copies of the PCIe reference clock. The new Si532xx family’s ultra-low jitter performance enables designers to cascade multiple buffers while still meeting the maximum allowable system PCIe jitter budget of 0.5ps RMS.
The Si532xx device output drivers leverage Silicon Labs’ push-pull HCSL technology, which eliminates the need for external termination resistors required by conventional PCIe buffers using constant-current output driver technology. Internal power filtering prevents power supply noise from degrading clock jitter performance, eliminating discrete low dropout regulators required by competing solutions. The Si532xx family supports both 85 and 100Ω impedance options.
“We’ve leveraged Silicon Labs’ expertise in high performance clock design to reduce jitter and power consumption in PCIe clock distribution applications,” said James Wilson, Senior Marketing Director for Silicon Labs’ timing products.
“Our new Si532xx family demonstrates Silicon Labs’ commitment to help consolidate and simplify high speed clock tree designs in data center, industrial, communications and consumer designs.”