Topics range from semi-damascene process optimisations and via resistance to hybrid bonding, backside connectivity, and electromigration-aware design strategies. Giulio Marti, R&D Engineer, and Blake Hodges, Superconducting Design Engineer at imec, are invited speakers. Furthermore, Zsolt Tokei, Fellow & Programme Director Nano-Interconnects at imec, and Christopher Wilson, Equipment and Material Supplier Portfolio Director at imec, will (co-)chair a session at the conference.
Highlights
Imec highlights the presentation on 16nm pitch Ru lines in semi-damascene with record-low resistance in a press release. The Ru lines had an average resistance as low as 656W/µm. The 16nm pitch metal lines were fabricated using a semi-damascene integration flow optimised for cost-effective manufacturability, making it an attractive approach for fabricating the first local interconnect metal layer of the A7 and beyond technology nodes.
See paper: “MP16/18 integration in Ru semi-damascene using SiN-based core for spacer-is-dielectric SADP”, G. Delie et al.
Imec contributions overview
2nd June
Zsolt Tokei, Fellow & Programme Director Nano-Interconnects at imec, will co-chair all presentations in Session 2 – Advanced Interconnects I (9.50am to 12pm)
- Session 2: Advanced Interconnects I “Advancing pillar-based FSAV integration of Ru interconnect to enlarge the process window and enable multi-layers of high-aspect ratio”, will be presented by Giulio Marti, R&D Engineer, as an invited speaker, from 10.15am to 10.40am. “Via resistance optimisation at advanced sub-2nm nodes”, will be presented by Assawer Soussou (Lam Research Corporation) et al. (co-authored by imec), from 10.40am to 11am. “Addressing integration challenges in direct backside contact of CFET”, will be presented by Cassie Sheng, R&D Engineer at imec, from 11.40am to 12pm. These results were created (in part) in the context of the NanoIC project.
- Session 3: 3D Packaging & Hybrid Bonding I “Evaluation of warpage tolerance of 100µm dies to achieve void-free bond and 100% assembly yield”, will be presented by Abhaysinha Patil, R&D Engineer – Wafer Assembly & Packaging at imec, from 1.55pm to 2.15pm. “Optimising direct die-to-wafer hybrid bonding: the role of scanner precorrection in achieving fine overlay performance”, will be presented by Imene Jadli, R&D Engineer at imec, from 2.45pm to 3.05pm.
- Session 4: Materials and Unit Process I “Ion beam deposition of ruthenium for interconnect applications in a direct metal etch approach”, will be presented by Rutvik J Mehta (Veeco Instruments Inc), co-authored by imec, from 3.50pm to 4.10pm. “UV surface pre-treatment and wet cleaning of ruthenium MP18 semi-damascene structures”, will be presented by Fulya Ulu Okudur, R&D Engineer at imec, from 4.10pm to 4.30pm. These results were created (in part) in the context of the NanoIC project.
4th June
- Session 6: Advanced Interconnects II “MP16/18 integration in Ru semi-damascene using SiN-based core for spacer-is-dielectric SADP”, will be presented by Gilles Delie, R&D Engineer at imec, from 9.45am to 10.05am. “Electrical test demonstration for 0.55 NA EUV single patterning damascene process”, will be presented by Stéphane Larivière (imec/TMC), from 10.25am to 10.45am.
- Session 7: Reliability and Characterisation “Quantifying the impact of thermal gradients on electromigration lifetimes in 90nm CD Cu Lines”, will be presented by Youqi Ding (KUL/imec), from 11.30am to 11.50am. “AI-driven variability-aware physics-based EM simulation framework for Jmax estimation”, will be presented by Ahmed Saleh (KUL/imec), from 11.50am to 12.10pm.
- Session 8: Materials and Unit Process II “The intermixing study of Cu/Ru interface in dual-damascene scheme for advanced interconnect”, will be presented by Sunyoung Noh (Samsung Electronics Co., Ltd.), co-authored by imec, from 3pm to 3.20pm.
- Session 9: Advanced Interconnects III “Integration of through-dielectric-via on buried power rail and slit nano through-silicon-via for enhanced backside connectivity”, will be presented by Peng Zhao, R&D Engineer at imec, from 4.20pm to 4.40pm. “Two-metal-level semi-damascene interconnect with variable width bottom metal at metal pitch 18-26nm and aspect ratio 4-6 routed using fully self-aligned via”, will be presented by Anshul Gupta, Principal Member of Technical Staff at imec, from 5pm to 5.20pm.
5th June
Christopher J Wilson, Equipment and Material Supplier Portfolio Director at imec, will chair all presentations in Session 11 – Advanced Interconnects IV, from 9.20am to 10.30am.
- Session 11: Advanced Interconnects IV “Optimised two metal level semi-damascene interconnects for superconducting digital logic”, will be presented by Blake Hodges, Superconducting Design Engineer at imec, as an invited speaker, from 9.45am to 10.10am.
- Session 12: BEOL Integration and Characterisation “Robust overlay control in 2-level semi-damascene”, will be presented by Yannick Hermans, R&D Engineer at imec, from 11.40am to 12pm. “Thermally-induced morphology changes in subtractive Ru lines and their mitigation”, will be presented by Houman Zahedmanesh, Principal Member of Technical Staff at imec, from 12pm to 12.20pm.
