Sunplus Reduces Design Cycle on High-Speed Multi-Million-Gate SoC Using Cadence Encounter Digital Implementation System

“With EDI System, we achieved greater productivity and faster time to market for our area-critical, high-performance 65-nanometer designs,” said Dr. Siuleong Yu, vice president and CTO of the Home Entertainment Business Unit at Sunplus. “EDI System enabled us to successfully tape out an advanced multimedia SoC design, involving the incredibly complex integration of multi-million gates into a single, low-power, area-efficient chip.”

Today’s consumer products are small, fast, feature-rich devices, that are driving the demand for larger-scale, higher-performance, complex low-power SoCs. To compete in this environment, Sunplus must deliver state-of-the-art differentiated designs faster than the competition. EDI System enables this by providing Sunplus with a high performance, high-capacity scalable end-to-end digital design solution to address the needs of high-density electronic design.

“Cadence EDI System, a key element of our Silicon Realization product line, delivers a significant advantage in productivity and predictability for complex advanced node semiconductor designs,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “It is exciting to help leading customers like Sunplus gain these advantages and to deliver new breakthrough high-definition home-entertainment products with superior quality and performance.”