GLOBALFOUNDRIES and Samsung Support New Cadence Virtuoso Advanced Node for 20- and 14nm Processes

“Moving to 20 and 14 nanometers presents numerous new manufacturing challenges, so we have been working closely with Cadence to help our mutual customers over the hurdles,” said Andy Brotman, vice president, Design Infrastructure at GLOBALFOUNDRIES. “Providing PDKs that meet customer demand for features like native SKILL PCells and real-time dynamic coloring is an essential element for the ecosystem to develop the foundation IP necessary to bring these new technologies to designers.”

“Manufacturing designs at Samsung’s 14-nanometer process requires advanced technology and methodologies that can tackle new requirements like double patterning and FinFETs,” said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions at Samsung Electronics. “With the Samsung-developed new SKILL-based PDK for our 14-nanometer process node, our customers can now improve design start-up time, boost designer productivity, and improve design quality.”

Virtuoso Advanced Node addresses the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. The new technology integrates seamlessly with the Cadence Integrated Physical Verification System (IPVS) —technology for DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations.

“Virtuoso Advanced Node provides many new functionalities to enable our customers’ designs at the most advanced nodes of 20 and 14 nanometers,” said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “And with their SKILL-based PDKs for these new process nodes, our foundry partners continue to provide the enablement necessary to ensure these complex designs will be successfully and profitably manufactured.”