Realtek integrates Cadence Tempus Timing

7th November 2023
Sheryl Miles

Cadence Design Systems has announced that Realtek has effectively deployed the Cadence Tempus Timing Solution for sign-off of an N12 high-performance CPU core, significantly enhancing power, performance, and area (PPA).

The adoption of the Tempus Timing Solution led to a twofold increase in productivity and a 50% reduction in design closure time compared to previous methodologies. Additionally, Realtek achieved a 50% reduction in both computing costs and memory requirements.

Key advantages provided to Realtek by the Tempus Timing Solution include:

  • Accurate golden signoff analysis: the Tempus Timing Solution, along with the Quantus Extraction Solution, provided Realtek with the assurance to deliver accurate, functioning silicon.
  • Enhanced productivity and schedule reduction: the Tempus ECO Option, incorporating SmartMMMC Optimisation, facilitated a quicker convergence of timing closure with fewer iterations within the Innovus Implementation System.
  • Compute resource efficiency: the Tempus CMMMC feature utilising concurrent multi-mode multi-corner technology enabled the execution of all scenarios in a single run, thereby hastening design closure and substantially conserving computing resources.

Yee-Wei Huang, Vice President at Realtek, stated: "Meeting our time-to-market deadlines with optimally performing parts is crucial to our business, and the Cadence Tempus Timing Solution helped us achieve those goals." He further noted the company's intentions following the collaboration: "Thanks to our successful N12 design project collaboration with Cadence, where we rapidly achieved working silicon, we plan to deploy the Tempus Timing Solution throughout multiple new projects across a wide range of technologies."

Sharad Mehrotra, Vice President, R&D in the Digital and Signoff Group at Cadence, emphasised the importance of efficiency in the design process: "With advanced node designs and increasing complexity, it’s important that customers like Realtek have a fast path to increase productivity, meet time-to-market deadlines, and achieve optimal PPA." He also acknowledged the success of the partnership: "By working closely with Realtek, we’ve validated that our timing signoff solutions strategy delivered on all the team’s key careabouts. Realtek has joined our growing list of signoff solution adopters, and we look forward to continuing our successful collaborations."

The Tempus Timing Solution is integral to Cadence's extensive digital flow, facilitating a swift journey to signoff and design tapeout. This tool and the overall digital flow are pivotal to Cadence’s Intelligent System Design strategy, accelerating excellence in SoC design.

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