An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDDhas risen above the threshold voltage VIT–. When the supply voltage drops below the threshold voltage VIT–, the output becomes active (low) again.
No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT&ndash, set by an internal voltage divider. The TPS382x-xx-Q1 family also offers watchdog time out options of 200ms (TPS3820-xx-Q1) and 1.6 s (TPS3823/4/8-xx-Q1).
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