Cadence Design Systems has announced that Cadence digital, signoff and custom/analogue tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for customers seeking to deploy 12FFC. In addition, Cadence IP is ready for design starts on the new 12FFC process.
With fully certified Cadence design tools and flows for the TSMC 12FFC process, systems and semiconductor companies can aggressively target emerging mid-range mobility and high-end consumer applications where performance is required within a more efficient area and power profile.
Cadence Tools for TSMC 12FFC Process Technology
The Cadence digital and signoff tools offer a number of floorplanning, placement, routing and extraction enhancements required for the 12FFC process technology, including improved pin access, rule compliance, electromigration (EM) fixing, via alignment/insertion and boundary cell handling. New enhancements since March 2017 include library cell placement for optimal timing closure and comprehensive support for routing halos. For custom/analogue, the Cadence Virtuoso Advanced Node Platform provides underlying support and capabilities for the TSMC 12FFC process, enabling better designer productivity over traditional manual approaches. Some of these features and capabilities include snapping grids for placement of devices, module generator (ModGen) array generation, advanced track patterns for routing, a wire editor, automatic routing features, and in-design design rule checks (DRCs).
Cadence digital, signoff and custom/analogue tools receiving v1.0 certification for 12FFC include the Innovus Implementation System, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS), LDE Electrical Analyser, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF option and Spectre Circuit Simulator, as well as the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analogue Design Environment and Virtuoso Integrated Physical Verification System.
In addition, the Cadence Virtuoso Liberate Characterisation Solution and the Virtuoso Variety Statistical Characterisation Solution have been validated to deliver accurate Liberty libraries for the TSMC 12FFC process including advanced timing, noise and power models.
Cadence IP for TSMC 12FFC Process Technology
In addition to the Cadence tools that have been optimised for the 12FFC process technology, a full suite of Cadence interface IP is under development to support this process. Cadence recently taped out its flagship 4266 speed-grade LPDDR4/4X PHY, which will be complemented by key Cadence mobility IP suites including MIPI DPHY, PCI Express 3.0 (PCIe3) PHY, USB3.1/USB2 PHY and DPv1.4 PHY IP. The mobility suites are targeted at application processors as well as high-end consumer and IoT applications.
“Mutual customers are demanding the flexibility of multiple performance versus cost points for each unique new SoC project,” said Dr. Anirudh Devgan, Executive Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “TSMC’s 12FFC process provides all the FinFET process benefits while offering better performance and differentiation. Cadence’s certification for version 1.0 of the 12FFC process signals our readiness to engage with mutual customers today on production designs using familiar tools and flows.”
“Our 12FFC process has gathered significant interest from customers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Our deep partnership with Cadence has enabled timely design solutions enablement, helping our customers adopt 12FFC to realise competitive advantages.”