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Tools
22nd June 2022
Codasip adds Veridify secure boot to RISC-V processors

Codasip has announced that quantum-resistant secure tools from Veridify Security Inc. are now available to support Codasip’s RISC-V processors with a secure-boot function. Veridify’s secure algorithm validates firmware as it loads onto the Codasip processor to reassure RISC-V developers that embedded systems are secure.

Appointments
2nd February 2022
Codasip appoints Functional Safety VP

Dave Higham’s expertise in ISO 26262 and security drives Codasip’s custom processor opportunities.

Design
23rd November 2021
Codasip adopts Imperas for RISC-V processor verification

Imperas Software and Codasip have announced that Codasip has adopted Imperas reference designs and the Imperas DV solution for Codasip IP.

Design
27th October 2021
Codasip boosts studio processor design tools with AXI automation

Codasip has announced further enhancements to its Studio processor design toolset. Features in Studio 9.1 include an expanded bus support with full AXI for high-performance designs, as well as improved support for LLVM and improved code density.

Design
1st February 2018
Studio 7 provides design and productivity tools for RISC-V processors

The launch of the 7th generation Codasip Studio, the IP-design and customisation software that allows for fast configuration and optimisation of RISC-V processors, customer-proprietary processor architectures, and their accompanying software development toolchains, has been announced by Codasip.

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