- Codasip Ltd.
612 00 Brno
- +420 541 141 475
Codasip and IAR demonstrate dual-core lockstep for RISC-V
Codasip and IAR deliver new possibilities for low-power embedded automotive applications through the award-winning Codasip L31 core and the safety-certified version of the development toolchain IAR Embedded Workbench for RISC-V.
embedded world 2023: Codasip presents on custom compute and RISC-V design
Codasip will present technical sessions on RISC-V together with partners Menta and Siemens at next month’s embedded world 2023.
Codasip launches SecuRISC5 initiative
Codasip launched SecuRISC5, a Codasip initiative to provide its customers with safe and secure custom compute using highly verified reference designs combining Codasip IP and third-party technology.
Codasip launches Codasip Labs
Codasip announced the establishment of Codasip Labs as an innovation hub within the company.
Codasip to showcase processor customisation
At RISC-V Summit 2022, Codasip will present solutions for implementing safety and security in RISC-V IP. In addition, the company will demonstrate the benefits of its unique processor customisation offering. The technology will be presented as demos in booth PG2 and in conference sessions.
Codasip to boost RISC-V security with Cerberus acquisition
Codasip, the leader in processor design automation and RISC-V processor IP, has announced that it has acquired Cerberus Security Labs. The company’s IoT security IP and experienced team will enable Codasip customers to quickly embed secure solutions for RISC-V processor designs.
Codasip joins OpenHW Group for RISC-V verification
Codasip has joined OpenHW Group. Together with the existing OpenHW ecosystem, Codasip will contribute to the development of standards across various techniques including formal verification. Codasip will contribute supporting IP, tools, and methodologies to help the wider community benefit from its experience in the development of high-quality, standard and customised RISC-V cores.
Codasip adds Veridify secure boot to RISC-V processors
Codasip has announced that quantum-resistant secure tools from Veridify Security Inc. are now available to support Codasip’s RISC-V processors with a secure-boot function. Veridify’s secure algorithm validates firmware as it loads onto the Codasip processor to reassure RISC-V developers that embedded systems are secure.
Codasip appoints Functional Safety VP
Dave Higham’s expertise in ISO 26262 and security drives Codasip’s custom processor opportunities.
Codasip adopts Imperas for RISC-V processor verification
Imperas Software and Codasip have announced that Codasip has adopted Imperas reference designs and the Imperas DV solution for Codasip IP.
Codasip boosts studio processor design tools with AXI automation
Codasip has announced further enhancements to its Studio processor design toolset. Features in Studio 9.1 include an expanded bus support with full AXI for high-performance designs, as well as improved support for LLVM and improved code density.
Studio 7 provides design and productivity tools for RISC-V processors
The launch of the 7th generation Codasip Studio, the IP-design and customisation software that allows for fast configuration and optimisation of RISC-V processors, customer-proprietary processor architectures, and their accompanying software development toolchains, has been announced by Codasip.