XIO1100’s flexible MAC interface supports both source synchronous and DDR clocking “This offers distinct advantages to our customers in terms of faster time to market and enabling lower cost solutions.” said Jawaid Ahmad, strategic product marketing manager for TI’s digital interface business unit. “SS clocking makes I/O layout robust and painless while DDR clocking offers our customers the opportunity to choose low-cost FPGAs which do not run faster than 125MHz.”
Adding to its list of benefits, the XIO1100 has an integrated adaptive equalizer in its receive link, providing system design flexibility and reliably increasing interconnect length supported by the XIO1100.
Availability, Package and Pricing
The XIO1100 is available today in a 100-pin MicroStar™ BGA in Pb or Pb-free RoHS-compliant package. 1KU reference price is $7/unit. TI also offers third-party development kits based on XIO1100 and Cyclone II™ or Spartan 3™ FPGAs.